[rtems commit] bsps/riscv: Always dispatch software interrupts

[Sebastian Huber]

Module:    rtems
Branch:    master
Commit:    ba53a177abd03e25eabb0ce7399c5aae2b134db9
Changeset: http://git.rtems.org/rtems/commit/?id=ba53a177abd03e25eabb0ce7399c5aae2b134db9

Author:    Sebastian Huber <sebastian.huber at embedded-brains.de>
Date:      Wed Nov  9 14:46:44 2022 +0100

bsps/riscv: Always dispatch software interrupts

This helps to run the interrupt API validation tests.

---

 bsps/riscv/riscv/irq/irq.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/bsps/riscv/riscv/irq/irq.c b/bsps/riscv/riscv/irq/irq.c
index c538447cb2..3f750e5c4c 100644
--- a/bsps/riscv/riscv/irq/irq.c
+++ b/bsps/riscv/riscv/irq/irq.c
@@ -99,7 +99,6 @@ void _RISCV_Interrupt_dispatch(uintptr_t mcause, Per_CPU_Control *cpu_self)
       __asm__ volatile ("fence o, i" : : : "memory");
     }
   } else if (mcause == (RISCV_INTERRUPT_SOFTWARE_MACHINE << 1)) {
-#ifdef RTEMS_SMP
     /*
      * Clear the software interrupt on this processor.  Synchronization of
      * inter-processor interrupts is done via Per_CPU_Control::message in
@@ -107,10 +106,10 @@ void _RISCV_Interrupt_dispatch(uintptr_t mcause, Per_CPU_Control *cpu_self)
      */
     *cpu_self->cpu_per_cpu.clint_msip = 0;
 
+#ifdef RTEMS_SMP
     _SMP_Inter_processor_interrupt_handler(cpu_self);
-#else
-    bsp_interrupt_handler_dispatch(RISCV_INTERRUPT_VECTOR_SOFTWARE);
 #endif
+    bsp_interrupt_handler_dispatch(RISCV_INTERRUPT_VECTOR_SOFTWARE);
   } else {
     bsp_fatal(RISCV_FATAL_UNEXPECTED_INTERRUPT_EXCEPTION);
   }