[rtems-lwip commit] rtemslwip: Resolve conflicts involving xparameters
Joel Sherrill
joel at rtems.org
Wed Feb 8 19:58:33 UTC 2023
Module: rtems-lwip
Branch: master
Commit: 383751a9cc85a911df3c4e756456c5a910452d6d
Changeset: http://git.rtems.org/rtems-lwip/commit/?id=383751a9cc85a911df3c4e756456c5a910452d6d
Author: Kinsey Moore <kinsey.moore at oarcorp.com>
Date: Thu Feb 2 15:05:16 2023 -0600
rtemslwip: Resolve conflicts involving xparameters
RTEMS recently imported drivers and their support code from Xilinx. This
has created a conflict with xparameters.h since it is now provided in
both RTEMS and RTEMS-lwIP. This moves the definitions provided by
xparameters.h in RTEMS-lwIP to xparameters_ps.h and adjusts its
accessibility to cover the same use cases.
---
rtemslwip/zynqmp/xemacps_g.c | 1 +
rtemslwip/zynqmp/xparameters.h | 113 --------------------------------
rtemslwip/zynqmp/xparameters_ps.h | 75 ++++++++++++++++++++-
rtemslwip/zynqmp_cfc400x/lwipbspopts.h | 2 +
rtemslwip/zynqmp_hardware/lwipbspopts.h | 2 +-
rtemslwip/zynqmp_qemu/lwipbspopts.h | 2 +-
6 files changed, 78 insertions(+), 117 deletions(-)
diff --git a/rtemslwip/zynqmp/xemacps_g.c b/rtemslwip/zynqmp/xemacps_g.c
index 3fc003b..471b080 100644
--- a/rtemslwip/zynqmp/xemacps_g.c
+++ b/rtemslwip/zynqmp/xemacps_g.c
@@ -25,6 +25,7 @@
*/
#include "xparameters.h"
+#include "xparameters_ps.h"
#include "xemacps.h"
/*
diff --git a/rtemslwip/zynqmp/xparameters.h b/rtemslwip/zynqmp/xparameters.h
deleted file mode 100644
index 053a154..0000000
--- a/rtemslwip/zynqmp/xparameters.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * Copyright (C) 2022 On-Line Applications Research Corporation (OAR)
- * Written by Kinsey Moore <kinsey.moore at oarcorp.com>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
- * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef XPARAMETERS_H
-#define XPARAMETERS_H
-
-/* Platform specific definitions */
-#define PLATFORM_ZYNQMP
-
-/* Definitions for driver EMACPS */
-#define XPAR_XEMACPS_NUM_INSTANCES 4
-
-/* Definitions for peripheral PSU_ETHERNET_0 */
-#define XPAR_PSU_ETHERNET_0_DEVICE_ID 0
-#define XPAR_PSU_ETHERNET_0_BASEADDR 0xFF0B0000
-#define XPAR_PSU_ETHERNET_0_ENET_CLK_FREQ_HZ 124998749
-#define XPAR_PSU_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0 12
-#define XPAR_PSU_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1 1
-#define XPAR_PSU_ETHERNET_0_ENET_SLCR_100MBPS_DIV0 60
-#define XPAR_PSU_ETHERNET_0_ENET_SLCR_100MBPS_DIV1 1
-#define XPAR_PSU_ETHERNET_0_ENET_SLCR_10MBPS_DIV0 60
-#define XPAR_PSU_ETHERNET_0_ENET_SLCR_10MBPS_DIV1 10
-
-/* Definitions for peripheral PSU_ETHERNET_1 */
-#define XPAR_PSU_ETHERNET_1_DEVICE_ID 1
-#define XPAR_PSU_ETHERNET_1_BASEADDR 0xFF0C0000
-#define XPAR_PSU_ETHERNET_1_ENET_CLK_FREQ_HZ 124998749
-#define XPAR_PSU_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0 12
-#define XPAR_PSU_ETHERNET_1_ENET_SLCR_1000MBPS_DIV1 1
-#define XPAR_PSU_ETHERNET_1_ENET_SLCR_100MBPS_DIV0 60
-#define XPAR_PSU_ETHERNET_1_ENET_SLCR_100MBPS_DIV1 1
-#define XPAR_PSU_ETHERNET_1_ENET_SLCR_10MBPS_DIV0 60
-#define XPAR_PSU_ETHERNET_1_ENET_SLCR_10MBPS_DIV1 10
-
-/* Definitions for peripheral PSU_ETHERNET_2 */
-#define XPAR_PSU_ETHERNET_2_DEVICE_ID 1
-#define XPAR_PSU_ETHERNET_2_BASEADDR 0xFF0D0000
-#define XPAR_PSU_ETHERNET_2_ENET_CLK_FREQ_HZ 124998749
-#define XPAR_PSU_ETHERNET_2_ENET_SLCR_1000MBPS_DIV0 12
-#define XPAR_PSU_ETHERNET_2_ENET_SLCR_1000MBPS_DIV1 1
-#define XPAR_PSU_ETHERNET_2_ENET_SLCR_100MBPS_DIV0 60
-#define XPAR_PSU_ETHERNET_2_ENET_SLCR_100MBPS_DIV1 1
-#define XPAR_PSU_ETHERNET_2_ENET_SLCR_10MBPS_DIV0 60
-#define XPAR_PSU_ETHERNET_2_ENET_SLCR_10MBPS_DIV1 10
-
-/******************************************************************/
-#define XPAR_PSU_ETHERNET_0_IS_CACHE_COHERENT 0
-#define XPAR_XEMACPS_0_IS_CACHE_COHERENT 0
-#define XPAR_PSU_ETHERNET_0_REF_CLK GEM0_REF
-#define XPAR_PSU_ETHERNET_1_IS_CACHE_COHERENT 0
-#define XPAR_XEMACPS_1_IS_CACHE_COHERENT 0
-#define XPAR_PSU_ETHERNET_1_REF_CLK GEM1_REF
-#define XPAR_PSU_ETHERNET_2_IS_CACHE_COHERENT 0
-#define XPAR_PSU_ETHERNET_2_REF_CLK GEM2_REF
-#define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 124998749
-#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1
-#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 1
-
-/* Definitions for peripheral PSU_ETHERNET_3 */
-#define XPAR_PSU_ETHERNET_3_DEVICE_ID 0
-#define XPAR_PSU_ETHERNET_3_BASEADDR 0xFF0E0000
-#define XPAR_PSU_ETHERNET_3_ENET_CLK_FREQ_HZ 124998749
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV0 12
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV1 1
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV0 60
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV1 1
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV0 60
-#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV1 10
-#define XPAR_PSU_ETHERNET_3_IS_CACHE_COHERENT 0
-#define XPAR_PSU_ETHERNET_3_REF_CLK GEM3_REF
-
-/* Canonical definitions for peripheral PSU_ETHERNET_0 */
-#define XPAR_XEMACPS_0_DEVICE_ID XPAR_PSU_ETHERNET_0_DEVICE_ID
-#define XPAR_XEMACPS_0_BASEADDR 0xFF0B0000
-
-/* Canonical definitions for peripheral PSU_ETHERNET_1 */
-#define XPAR_XEMACPS_1_DEVICE_ID XPAR_PSU_ETHERNET_1_DEVICE_ID
-#define XPAR_XEMACPS_1_BASEADDR 0xFF0C0000
-
-/* Canonical definitions for peripheral PSU_ETHERNET_2 */
-#define XPAR_XEMACPS_2_DEVICE_ID XPAR_PSU_ETHERNET_2_DEVICE_ID
-#define XPAR_XEMACPS_2_BASEADDR 0xFF0D0000
-
-/* Canonical definitions for peripheral PSU_ETHERNET_3 */
-#define XPAR_XEMACPS_3_DEVICE_ID XPAR_PSU_ETHERNET_3_DEVICE_ID
-#define XPAR_XEMACPS_3_BASEADDR 0xFF0E0000
-
-#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF9010000U
-
-#endif
diff --git a/rtemslwip/zynqmp/xparameters_ps.h b/rtemslwip/zynqmp/xparameters_ps.h
index 427ae77..0defb9d 100644
--- a/rtemslwip/zynqmp/xparameters_ps.h
+++ b/rtemslwip/zynqmp/xparameters_ps.h
@@ -36,8 +36,6 @@
#define XPAR_XEMACPS_3_INTR XPS_GEM3_INT_ID
#define XPAR_XEMACPS_3_WAKE_INTR XPS_GEM3_WAKE_INT_ID
-#define XPS_SYS_CTRL_BASEADDR 0xFF180000U
-
#define XPS_GEM0_INT_ID ( 57U + 32U )
#define XPS_GEM0_WAKE_INT_ID ( 58U + 32U )
#define XPS_GEM1_INT_ID ( 59U + 32U )
@@ -65,4 +63,77 @@
#define XPAR_PSU_ETHERNET_3_INTERRUPT_ID 0x403FU
#define XPAR_PSU_ETHERNET_3_WAKE_INTERRUPT_ID 0x403FU
+/* Platform specific definitions */
+#define PLATFORM_ZYNQMP
+
+/* Definitions for driver EMACPS */
+#define XPAR_XEMACPS_NUM_INSTANCES 4
+
+/* Definitions for peripheral PSU_ETHERNET_0 */
+#define XPAR_PSU_ETHERNET_0_DEVICE_ID 0
+#define XPAR_PSU_ETHERNET_0_BASEADDR 0xFF0B0000
+#define XPAR_PSU_ETHERNET_0_ENET_CLK_FREQ_HZ 124998749
+#define XPAR_PSU_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0 12
+#define XPAR_PSU_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1 1
+#define XPAR_PSU_ETHERNET_0_ENET_SLCR_100MBPS_DIV0 60
+#define XPAR_PSU_ETHERNET_0_ENET_SLCR_100MBPS_DIV1 1
+#define XPAR_PSU_ETHERNET_0_ENET_SLCR_10MBPS_DIV0 60
+#define XPAR_PSU_ETHERNET_0_ENET_SLCR_10MBPS_DIV1 10
+#define XPAR_PSU_ETHERNET_0_IS_CACHE_COHERENT 0
+#define XPAR_PSU_ETHERNET_0_REF_CLK GEM0_REF
+#define XPAR_XEMACPS_0_IS_CACHE_COHERENT 0
+#define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 124998749
+#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1
+#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 1
+#define XPAR_XEMACPS_0_DEVICE_ID XPAR_PSU_ETHERNET_0_DEVICE_ID
+#define XPAR_XEMACPS_0_BASEADDR 0xFF0B0000
+
+/* Definitions for peripheral PSU_ETHERNET_1 */
+#define XPAR_PSU_ETHERNET_1_DEVICE_ID 1
+#define XPAR_PSU_ETHERNET_1_BASEADDR 0xFF0C0000
+#define XPAR_PSU_ETHERNET_1_ENET_CLK_FREQ_HZ 124998749
+#define XPAR_PSU_ETHERNET_1_ENET_SLCR_1000MBPS_DIV0 12
+#define XPAR_PSU_ETHERNET_1_ENET_SLCR_1000MBPS_DIV1 1
+#define XPAR_PSU_ETHERNET_1_ENET_SLCR_100MBPS_DIV0 60
+#define XPAR_PSU_ETHERNET_1_ENET_SLCR_100MBPS_DIV1 1
+#define XPAR_PSU_ETHERNET_1_ENET_SLCR_10MBPS_DIV0 60
+#define XPAR_PSU_ETHERNET_1_ENET_SLCR_10MBPS_DIV1 10
+#define XPAR_PSU_ETHERNET_1_IS_CACHE_COHERENT 0
+#define XPAR_PSU_ETHERNET_1_REF_CLK GEM1_REF
+#define XPAR_XEMACPS_1_IS_CACHE_COHERENT 0
+#define XPAR_XEMACPS_1_DEVICE_ID XPAR_PSU_ETHERNET_1_DEVICE_ID
+#define XPAR_XEMACPS_1_BASEADDR 0xFF0C0000
+
+/* Definitions for peripheral PSU_ETHERNET_2 */
+#define XPAR_PSU_ETHERNET_2_DEVICE_ID 1
+#define XPAR_PSU_ETHERNET_2_BASEADDR 0xFF0D0000
+#define XPAR_PSU_ETHERNET_2_ENET_CLK_FREQ_HZ 124998749
+#define XPAR_PSU_ETHERNET_2_ENET_SLCR_1000MBPS_DIV0 12
+#define XPAR_PSU_ETHERNET_2_ENET_SLCR_1000MBPS_DIV1 1
+#define XPAR_PSU_ETHERNET_2_ENET_SLCR_100MBPS_DIV0 60
+#define XPAR_PSU_ETHERNET_2_ENET_SLCR_100MBPS_DIV1 1
+#define XPAR_PSU_ETHERNET_2_ENET_SLCR_10MBPS_DIV0 60
+#define XPAR_PSU_ETHERNET_2_ENET_SLCR_10MBPS_DIV1 10
+#define XPAR_PSU_ETHERNET_2_IS_CACHE_COHERENT 0
+#define XPAR_PSU_ETHERNET_2_REF_CLK GEM2_REF
+#define XPAR_XEMACPS_2_DEVICE_ID XPAR_PSU_ETHERNET_2_DEVICE_ID
+#define XPAR_XEMACPS_2_BASEADDR 0xFF0D0000
+
+/* Definitions for peripheral PSU_ETHERNET_3 */
+#define XPAR_PSU_ETHERNET_3_DEVICE_ID 0
+#define XPAR_PSU_ETHERNET_3_BASEADDR 0xFF0E0000
+#define XPAR_PSU_ETHERNET_3_ENET_CLK_FREQ_HZ 124998749
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV0 12
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_1000MBPS_DIV1 1
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV0 60
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_100MBPS_DIV1 1
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV0 60
+#define XPAR_PSU_ETHERNET_3_ENET_SLCR_10MBPS_DIV1 10
+#define XPAR_PSU_ETHERNET_3_IS_CACHE_COHERENT 0
+#define XPAR_PSU_ETHERNET_3_REF_CLK GEM3_REF
+#define XPAR_XEMACPS_3_DEVICE_ID XPAR_PSU_ETHERNET_3_DEVICE_ID
+#define XPAR_XEMACPS_3_BASEADDR 0xFF0E0000
+
+#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF9010000U
+
#endif
diff --git a/rtemslwip/zynqmp_cfc400x/lwipbspopts.h b/rtemslwip/zynqmp_cfc400x/lwipbspopts.h
index 27eb6a9..00f8077 100644
--- a/rtemslwip/zynqmp_cfc400x/lwipbspopts.h
+++ b/rtemslwip/zynqmp_cfc400x/lwipbspopts.h
@@ -27,6 +27,8 @@
#ifndef RTEMSLWIP_LWIPBSPOPTS_H
#define RTEMSLWIP_LWIPBSPOPTS_H
+#include <xparameters_ps.h>
+
/* Use SGMII mode for all interfaces on the CFC-400X */
#define ZYNQMP_USE_SGMII
diff --git a/rtemslwip/zynqmp_hardware/lwipbspopts.h b/rtemslwip/zynqmp_hardware/lwipbspopts.h
index d35e631..a3acc19 100644
--- a/rtemslwip/zynqmp_hardware/lwipbspopts.h
+++ b/rtemslwip/zynqmp_hardware/lwipbspopts.h
@@ -1 +1 @@
-/* This file is a stub and intentionally left blank */
+#include <xparameters_ps.h>
diff --git a/rtemslwip/zynqmp_qemu/lwipbspopts.h b/rtemslwip/zynqmp_qemu/lwipbspopts.h
index d35e631..a3acc19 100644
--- a/rtemslwip/zynqmp_qemu/lwipbspopts.h
+++ b/rtemslwip/zynqmp_qemu/lwipbspopts.h
@@ -1 +1 @@
-/* This file is a stub and intentionally left blank */
+#include <xparameters_ps.h>
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