[rtems-central commit] spec: Fix FTMCTRL - MCFG1 bit fields

[Sebastian Huber]

Module:    rtems-central
Branch:    master
Commit:    a7c2836a78cd97686e937d584df5210cdb07e90a
Changeset: http://git.rtems.org/rtems-central/commit/?id=a7c2836a78cd97686e937d584df5210cdb07e90a

Author:    Sebastian Huber <sebastian.huber at embedded-brains.de>
Date:      Thu Feb 16 09:01:08 2023 +0100

spec: Fix FTMCTRL - MCFG1 bit fields

There was an off by one error in all bit fields.  Add the R flag.

Update #4842.

---

 spec/dev/grlib/if/ftmctrl.yml | 44 ++++++++++++++++++++++++-------------------
 1 file changed, 25 insertions(+), 19 deletions(-)

diff --git a/spec/dev/grlib/if/ftmctrl.yml b/spec/dev/grlib/if/ftmctrl.yml
index 329c8042..31cbf6bc 100644
--- a/spec/dev/grlib/if/ftmctrl.yml
+++ b/spec/dev/grlib/if/ftmctrl.yml
@@ -45,74 +45,80 @@ registers:
       brief: null
       description: null
       name: 'PBRDY'
-      start: 31
-      width: 1
-    - access: [r, w]
-      brief: null
-      description: null
-      name: 'ABRDY'
       start: 30
       width: 1
     - access: [r, w]
       brief: null
       description: null
-      name: 'IOBUSW'
+      name: 'ABRDY'
       start: 29
       width: 1
     - access: [r, w]
       brief: null
       description: null
-      name: 'IBRDY'
+      name: 'IOBUSW'
       start: 27
       width: 2
     - access: [r, w]
       brief: null
       description: null
-      name: 'BEXCN'
+      name: 'IBRDY'
       start: 26
       width: 1
     - access: [r, w]
       brief: null
       description: null
-      name: 'IO_WAITSTATES'
-      start: 24
+      name: 'BEXCN'
+      start: 25
       width: 1
     - access: [r, w]
       brief: null
       description: null
-      name: 'IOEN'
+      name: 'IO_WAITSTATES'
       start: 20
       width: 4
     - access: [r, w]
       brief: null
       description: null
-      name: 'ROMBANKSZ'
+      name: 'IOEN'
       start: 19
       width: 1
+    - access: [r]
+      brief: null
+      description: null
+      name: 'R'
+      start: 18
+      width: 1
     - access: [r, w]
       brief: null
       description: null
-      name: 'PWEN'
+      name: 'ROMBANKSZ'
       start: 14
       width: 4
+    - access: [r, w]
+      brief: null
+      description: null
+      name: 'PWEN'
+      start: 11
+      width: 1
     - access: [r, w]
       brief: null
       description: null
       name: 'PROM_WIDTH'
-      start: 12
+      start: 8
       width: 2
     - access: [r, w]
       brief: null
       description: null
       name: 'PROM_WRITE_WS'
-      start: 11
-      width: 1
+      start: 4
+      width: 4
     - access: [r, w]
       brief: null
       description: null
       name: 'PROM_READ_WS'
-      start: 8
-      width: 2
+      start: 0
+      width: 4
     variants: []
   brief: |
     Memory configuration register 1