[rtems commit] bsps/xqspipsu: Handle SMP systems properly

[Joel Sherrill]

Module:    rtems
Branch:    master
Commit:    333fd02631196f5d0034903f8634bcced32684d0
Changeset: http://git.rtems.org/rtems/commit/?id=333fd02631196f5d0034903f8634bcced32684d0

Author:    Kinsey Moore <kinsey.moore at oarcorp.com>
Date:      Wed Jun 21 10:47:33 2023 -0500

bsps/xqspipsu: Handle SMP systems properly

The NOR driver was not written with SMP systems and caching in mind.
This makes the IsBusy flag volatile for updates across cores and
introduces cache flushing and invalidation where necessary for data
manipulated by the DMA engine in the QSPI peripheral.

---

 bsps/include/dev/spi/xqspipsu.h             |  3 +++
 bsps/shared/dev/spi/xqspipsu-flash-helper.c |  3 +++
 bsps/shared/dev/spi/xqspipsu.c              | 23 +++++++++++++++++++++++
 3 files changed, 29 insertions(+)

diff --git a/bsps/include/dev/spi/xqspipsu.h b/bsps/include/dev/spi/xqspipsu.h
index 7d9b662464..92d38eb0c8 100644
--- a/bsps/include/dev/spi/xqspipsu.h
+++ b/bsps/include/dev/spi/xqspipsu.h
@@ -259,6 +259,9 @@ typedef struct {
 	s32 TxBytes;	 /**< Number of bytes to transfer (state) */
 	s32 RxBytes;	 /**< Number of bytes left to transfer(state) */
 	s32 GenFifoEntries;	 /**< Number of Gen FIFO entries remaining */
+#ifdef __rtems__
+	volatile
+#endif
 	u32 IsBusy;		 /**< A transfer is in progress (state) */
 	u32 ReadMode;		 /**< DMA or IO mode */
 	u32 GenFifoCS;		/**< Gen FIFO chip selection */
diff --git a/bsps/shared/dev/spi/xqspipsu-flash-helper.c b/bsps/shared/dev/spi/xqspipsu-flash-helper.c
index 4e018bf2fa..c9d8273b87 100644
--- a/bsps/shared/dev/spi/xqspipsu-flash-helper.c
+++ b/bsps/shared/dev/spi/xqspipsu-flash-helper.c
@@ -314,6 +314,7 @@ static int FlashReadID(XQspiPsu *QspiPsuPtr)
   }
   while (TransferInProgress);
 
+  rtems_cache_invalidate_multiple_data_lines(ReadBfrPtr, 3);
   /* In case of dual, read both and ensure they are same make/size */
 
   /*
@@ -860,6 +861,7 @@ int QspiPsu_NOR_Read(
     while (TransferInProgress);
 
   }
+  rtems_cache_invalidate_multiple_data_lines(ReadBuffer, ByteCount);
   return 0;
 }
 
@@ -1047,6 +1049,7 @@ static int MultiDieRead(
     Address += data_len;
     remain_len -= data_len;
   }
+  rtems_cache_invalidate_multiple_data_lines(ReadBfrPtr, ByteCount);
   return 0;
 }
 
diff --git a/bsps/shared/dev/spi/xqspipsu.c b/bsps/shared/dev/spi/xqspipsu.c
index 1286efd359..c77407bdf4 100644
--- a/bsps/shared/dev/spi/xqspipsu.c
+++ b/bsps/shared/dev/spi/xqspipsu.c
@@ -84,6 +84,9 @@
 #include "xqspipsu.h"
 #include "xqspipsu_control.h"
 #include "sleep.h"
+#ifdef __rtems__
+#include <rtems/rtems/cache.h>
+#endif
 
 /************************** Constant Definitions *****************************/
 #define MAX_DELAY_CNT	10000000U	/**< Max delay count */
@@ -442,7 +445,16 @@ s32 XQspiPsu_PolledTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
 
 	for (Index = 0; Index < (s32)NumMsg; Index++) {
 		Xil_AssertNonvoid(Msg[Index].ByteCount > 0U);
+#ifdef __rtems__
+		if (Msg[Index].TxBfrPtr != NULL) {
+			rtems_cache_flush_multiple_data_lines(Msg[Index].TxBfrPtr, Msg[Index].ByteCount);
+		}
+#endif
 	}
+#ifdef __rtems__
+	rtems_cache_flush_multiple_data_lines(Msg, NumMsg * sizeof(*Msg));
+#endif
+
 	/*
 	 * Check whether there is another transfer in progress.
 	 * Not thread-safe
@@ -582,7 +594,18 @@ s32 XQspiPsu_InterruptTransfer(XQspiPsu *InstancePtr, XQspiPsu_Msg *Msg,
 	Xil_AssertNonvoid(InstancePtr->IsReady == XIL_COMPONENT_IS_READY);
 
 	for (Index = 0; Index < (s32)NumMsg; Index++)
+#ifdef __rtems__
+	{
+#endif
 		Xil_AssertNonvoid(Msg[Index].ByteCount > 0U);
+#ifdef __rtems__
+		if (Msg[Index].TxBfrPtr != NULL) {
+			rtems_cache_flush_multiple_data_lines(Msg[Index].TxBfrPtr, Msg[Index].ByteCount);
+		}
+	}
+	rtems_cache_flush_multiple_data_lines(Msg, NumMsg * sizeof(*Msg));
+#endif
+
 	/*
 	 * Check whether there is another transfer in progress.
 	 * Not thread-safe