[PATCH 0/3] Update to the ZynqMP Cortex-R5 RPU work

[Philip Kirkpatrick]

Kinsey,

Nope, no overstepping.  I've been wanting to finish this off but there has
always been something else higher on my to do list these past few months.
I'm more than happy for someone else to take over.  Since you are pushing
on this, I'll try to get the patch for the cache together.  I'm just going
to give you what I have and not rebase or modify from your changes, because
if I try to do that you probably won't see it until January.  I haven't
reviewed your changes, so you may need to make some edits to the cache
patch for it to work with your code.  Since the ZynqMP uses DDR memory, the
performance without the cache is pretty terrible (about a factor of 10 with
vs without).

-Phil

On Wed, Sep 27, 2023 at 7:26 PM Kinsey Moore <kinsey.moore at oarcorp.com>
wrote:

> This patch set addresses all outstanding comments on the v2 patch from
> Philip Kirkpatrick and moves the BSP to use the existing Xilinx support
> code that the AArch64 ZynqMP BSP uses.
>
> Philip,
> Hopefully this isn't overstepping, but there's some renewed interest in
> this work and I figured I'd see if I could get it moving again.
>
> Kinsey
>
>
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