[Bug 2003] Instruction cache problem in gen5200 bsps

[bugzilla-daemon at rtems.org]

https://www.rtems.org/bugzilla/show_bug.cgi?id=2003

--- Comment #5 from ktaylan at gmail.com 2012-02-02 00:30:12 CST ---
Ok i will provide the patch. 
Actually we are evaluating to use RTEMS in our applications.
During evaluation we made some scratch works on Phytec MPC5200B I/O boards that
we have already use.(We are planing to integrate this bsp to main repo but
first some clean work is required)
In our native applications if we want to use instruction cache we always sets
ibats. Otherwise we are getting machine check exception interrupt.(Actually
ibats are required because there are two independent caches, instruction and
data caches) I am not talking about setting MSR_IR bit. This is the first step.
According to e300 Power Architecture Core Family Reference Manual rev4 ICE bit
should also be set in HID0 register. But if this is done without setting ibats,
machine check exception occurs. According to the manuals, it is recommended to
invalidate the cache before first time use. This is because ICFI bit was set.
After setting the ICFI bit, it should be cleared if we don't want to get cache
miss. Actually if ICFI bit wasn't cleared instruction cache doesn't work.

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