[Bug 2003] Instruction cache problem in gen5200 bsps

bugzilla-daemon at rtems.org bugzilla-daemon at rtems.org
Wed Feb 1 14:45:24 UTC 2012


--- Comment #4 from Sebastian Huber <sebastian.huber at embedded-brains.de> 2012-02-01 08:45:24 CST ---
The instruction cache is on since we don't set the MSR_IR bit.  You have to set
up the IBATs only then we set the MSR_IR bit.  See e300 core manual section
4.4.1 "Memory/Cache Access Attributes (WIMG Bits)".

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