[Bug 2003] Instruction cache problem in gen5200 bsps

[bugzilla-daemon at rtems.org]

https://www.rtems.org/bugzilla/show_bug.cgi?id=2003

--- Comment #4 from Sebastian Huber <sebastian.huber at embedded-brains.de> 2012-02-01 08:45:24 CST ---
The instruction cache is on since we don't set the MSR_IR bit.  You have to set
up the IBATs only then we set the MSR_IR bit.  See e300 core manual section
4.4.1 "Memory/Cache Access Attributes (WIMG Bits)".

-- 
Configure bugmail: https://www.rtems.org/bugzilla/userprefs.cgi?tab=email
------- You are receiving this mail because: -------
You are watching all bug changes.