[RTEMS Project] #3785: Add RISC-V BSP with support for the Freedom E310 Arty A7 FPGA

[RTEMS trac]

#3785: Add RISC-V BSP with support for the Freedom E310 Arty A7 FPGA
-------------------------------------------+---------------------
 Reporter:  pragnesh                       |       Owner:  (none)
     Type:  task                           |      Status:  new
 Priority:  normal                         |   Milestone:  5.1
Component:  arch/riscv                     |     Version:  5
 Severity:  normal                         |  Resolution:
 Keywords:  #RISCV, #FREEDOME310, #ARTYA7  |  Blocked By:
 Blocking:                                 |
-------------------------------------------+---------------------

Comment (by pragnesh):

 Link for the hardware and manuals

 - https://www.sifive.com/documentation (Freedom FE310-G002 Manual)
 -
 https://www.digikey.com/eewiki/display/LOGIC/Digilent+Arty+A7+with+Xilinx+Artix-7+Implementing+SiFive+FE310+RISC-V
 - https://sifive.cdn.prismic.io/sifive%2Fed96de35-065f-
 474c-a432-9f6a364af9c8_sifive-e310-arty-gettingstarted-v1.0.6.pdf

--
Ticket URL: <http://devel.rtems.org/ticket/3785#comment:3>
RTEMS Project <http://www.rtems.org/>
RTEMS Project