[RTEMS Project] #3785: Add RISC-V BSP with support for the Freedom E310 Arty A7 FPGA

[RTEMS trac]

#3785: Add RISC-V BSP with support for the Freedom E310 Arty A7 FPGA
-------------------------------------------+---------------------
 Reporter:  pragnesh                       |       Owner:  (none)
     Type:  task                           |      Status:  new
 Priority:  normal                         |   Milestone:  5.1
Component:  arch/riscv                     |     Version:  5
 Severity:  normal                         |  Resolution:
 Keywords:  #RISCV, #FREEDOME310, #ARTYA7  |  Blocked By:
 Blocking:                                 |
-------------------------------------------+---------------------

Comment (by Sebastian Huber <sebastian.huber@…>):

 In [changeset:"df9426f970c6c3ff11300cefbf221abee679b270/rtems"
 df9426f/rtems]:
 {{{
 #!CommitTicketReference repository="rtems"
 revision="df9426f970c6c3ff11300cefbf221abee679b270"
 bsp/riscv: riscv_get_core_frequency()

 Always provide this function.  Return 0 by default.  Fix formatting.
 Simplify function.

 Update #3785.
 }}}

--
Ticket URL: <http://devel.rtems.org/ticket/3785#comment:5>
RTEMS Project <http://www.rtems.org/>
RTEMS Project