Documentation | Draft: Add Intel NIOS V BSP to RISC-V section of user's manual (!39)

[Joel Sherrill (@joel)]

Merge request https://gitlab.rtems.org/rtems/docs/rtems-docs/-/merge_requests/39 was reviewed by Joel Sherrill

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Joel Sherrill started a new discussion on user/bsps/bsps-riscv.rst: https://gitlab.rtems.org/rtems/docs/rtems-docs/-/merge_requests/39#note_110894

 > +
 > +This BSP supports the `NIOS V <https://www.intel.com/content/www/us/en/products/details/fpga/intellectual-property/processors-peripherals/niosv.html>`_
 > +systems from Intel. The NIOS V is a synthesizable verilog model of a processor

Capitalise Verilog

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Joel Sherrill started a new discussion on user/bsps/bsps-riscv.rst: https://gitlab.rtems.org/rtems/docs/rtems-docs/-/merge_requests/39#note_110895

 > +     (false by default).
 > +
 > +``NIOSV_HAS_FP``

Does this impact the multilib used? 

On other architectures, this is detected via cpp predefines from GCC and on the RISC-V, it looks the same. Looking at riscv-context-switch.S, it appears that (__riscv_flen > 0) is used to enable the FP context switch.




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