RTEMS | Add BSP for BeagleV-Fire board (!194)

[Francescodario Cuzzocrea (@fcuzzocrea)]

Francescodario Cuzzocrea commented on a discussion on bsps/riscv/shared/start/bspgetworkarea.c: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/194#note_112113

 >    int ac;
 >    int sc;
 >    int len;
 > +  uint64_t start64;
 > +  uint64_t size64;
 > +  uint64_t start32;
 > +  uint64_t size32;

@joel indeed you are super right! Since Polarfire SoC FPGA is basically an FPGA with an ASIC inside (which is the Microprocessor SubSystem, the MSS) and the ASIC is configured using the Polarfire SoC configurator (which comes as part of Libero SoC), the user must always look at the Libero design to understand how it is configured the SoC and if there is any soft-ip core.

-- 
View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/194#note_112113
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