RTEMS | aarch64: The FPSCR (FPSR/FPCR) and FPEXC registers do not have thread storage (#5214)

[Kinsey Moore (@opticron)]

Kinsey Moore commented: https://gitlab.rtems.org/rtems/rtos/rtems/-/issues/5214#note_119870


As per the AArch64 Procedure Call Specification available from the [official ARM repository](https://github.com/ARM-software/abi-aa/releases/download/2024Q3/aapcs64.pdf), FPSR and FPCR are not callee-saved and can not be expected to survive a function call which is required for non-IRQ context switches. IRQ-based context switches save the FPCR and FPSR as part of the interrupt frame and restore them correctly.

As per section 6.1.2 of the above referenced document:
```
The FPSR is a status register that holds the cumulative exception bits of the floating-point unit. It contains the fields IDC, IXC, UFC, OFC, DZC, IOC and QC. These fields are not preserved across a public interface and may have any value on entry to a subroutine.
```

A public interface is implied in the scope (section 3) and elsewhere to be a function accessible outside of its translation unit.

Given that I've already discussed this with you at length, I'll let someone else weight in.

As I've stated before, if you have a test case that demonstrates failure to preserve FPSR across IRQ-based context switches or official documentation from ARM that declares FPSR as callee-saved, I'd be happy to take a look at what's going on or re-evaluation my position.

@chris Could you review this issue?

-- 
View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/issues/5214#note_119870
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