RTEMS | aarch64: The FPSCR (FPSR/FPCR) and FPEXC registers do not have thread storage (#5214)

[Joel Sherrill (@joel)]

Joel Sherrill commented on a discussion: https://gitlab.rtems.org/rtems/rtos/rtems/-/issues/5214#note_119872


Preemption can be initiated two ways but both end up logically being calls to _Thread_Dispatch -> _CPU_Context_Switch which means it is a call and follows normal calling conventions. Preemption can occur:

1. By a thread caller making a higher priority thread ready. This is a thread-to-thread context switch and there is no need to preserve scratch registers which are not guaranteed to be preserved across the call. 
2. By an ISR calling a function making a thread higher priority than the thread interrupted. It is part of the ISR's responsibility to preserve any registers a called method can modify. Normally ISRs do not use the FPU but (as @opticron points out), the FPSR would have to be preserved.

I think @opticron is correct based on ARM's documentation.

-- 
View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/issues/5214#note_119872
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