RTEMS | RISC-V: Add Smdbltrp extension compatibility (!538)

[Matteo Concas (@matteo.concas)]

Matteo Concas created a merge request: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/538

Project:Branches: matteo.concas/rtems-gaisler:matteo/add-Smdbltrp-compat to rtems/rtos/rtems:main
Author:   Matteo Concas




## Summary

cpu/riscv: Add Smdbltrp extension compatibility

If the Double Trap Extension is implemented, the MDT bit of the mstatus (or mstatush in RV32) register will be set when a trap is to be taken.

The MIE (Machine Interrupt Enable) bit can only be set to 1 if the MDT bit is zero.

Thus, we need to clear MDT first if we want to enable interrupts when dispatching a thread.

MDT is also cleared in register `a1` before restoring the interrupt frame as writing 1 to MDT will cause MIE to be set to 0. In RV64 this happens regardless of the value written to MIE in the same write.

In RV32, MDT is in mstatush so we do not need to clear during restore as this register is not restored.

With this change all 60 SMP tests pass (compared to 20/60 before the fix). The tests have been run on hardware using two RV64 CPUs that implement the double trap extension.

Update #5274

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View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/538
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