RTEMS | RISC-V implementation does not support Smdbltrp extension (#5274)

[Matteo Concas (@matteo.concas)]

Matteo Concas commented on a discussion: https://gitlab.rtems.org/rtems/rtos/rtems/-/issues/5274#note_136202


In the case I described above the value of NMIE doesn't seem to matter (From ["Smrnmi" Extension for Resumable Non-Maskable Interrupts, Version 1.0](https://docs.riscv.org/reference/isa/priv/rnmi.html#rnmi)):
> If the hart encounters an exception while executing in M-mode with the mnstatus.NMIE bit clear, the actions taken are the same as if the exception had occurred while mnstatus.NMIE were set, except that the program counter is set to the RNMI exception trap handler address.

To be clear, in our case the NMIE bit is never set by RTEMS as the RISC-V BSP has no knowledge of it. So encountering an exception while in the exception handler should always means we end up in the RNMI exception handler (also, some RV implementations could decide for the exception and normal handlers to be the same thing and only implement one CSR for its address).

I think a separate discussion around normal RNMI handling could also be had, this just came about as I encountered that situation (trap-in-trap) while doing some testing and couldn't understand why the PC was being set to an unexpected address :smile:

-- 
View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/issues/5274#note_136202
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