RTEMS | RISC-V: Add support for ESP32-C3 (!1160)

Wed Apr 1 00:55:17 UTC 2026

Kinsey Moore commented on a discussion on cpukit/score/cpu/riscv/riscv-exception-handler.S: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1160#note_147703

 > +	/*
 > +	 * Vectored exception/interrupt handlers can require the vector base to
 > +	 * be aligned to 256 bytes
 > +	 */
 > +	.align	8
 >  	.option	arch, +zicsr
 >  
 > -TYPE_FUNC(_RISCV_Exception_handler)
 > -SYM(_RISCV_Exception_handler):
 > +/*
 > + * This could be a nop slide, but it would introduce additional latency into
 > + * interrupt handling depending on which interrupt was triggered
 > + */
 > +TYPE_FUNC(_RISCV_Vector_table)
 > +SYM(_RISCV_Vector_table):
 > +	j .LRISCV_Exception_handler

Thanks, done.

-- 
View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1160#note_147703
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