RTEMS | RISC-V: Add support for ESP32-C3 (!1160)

Wed Apr 1 00:55:41 UTC 2026

Kinsey Moore commented on a discussion on bsps/riscv/esp32/irq/irq_c3.c: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1160#note_147711

 > +
 > +void bsp_interrupt_facility_initialize(void)
 > +{
 > +  /*
 > +   * Enable all interrupt matrix output channels, all interrupt control is done
 > +   * via mapping in the interrupt matrix
 > +   */
 > +  uint32_t cookie = riscv_interrupt_disable();
 > +
 > +  /* Enable all cpu-side interrupts */
 > +  MATRIX_REG( INTERRUPT_CORE0_CPU_INT_ENABLE_REG ) = 0xffffffffU;
 > +  /* Set everything to level interrupts */
 > +  MATRIX_REG( INTERRUPT_CORE0_CPU_INT_TYPE_REG ) = 0x0U;
 > +  for (uint8_t vec = 1; vec < RISCV_MAXIMUM_EXTERNAL_INTERRUPTS; vec++) {
 > +    /*
 > +     * RISCV_MAXIMUM_EXTERNAL_INTERRUPTS is a valid interrupt because 0 is

The comment below is outdated. I adjusted the external interrupt count up to include 0 as it makes other handling simpler. `vec <` is correct.

-- 
View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1160#note_147711
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