RTEMS | RISC-V: Add support for ESP32-C3 (!1160)

Wed Apr 1 00:55:39 UTC 2026

Kinsey Moore commented on a discussion on bsps/riscv/esp32/irq/irq_c3.c: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1160#note_147710

 > +  /* Set everything to level interrupts */
 > +  MATRIX_REG( INTERRUPT_CORE0_CPU_INT_TYPE_REG ) = 0x0U;
 > +  for (uint8_t vec = 1; vec < RISCV_MAXIMUM_EXTERNAL_INTERRUPTS; vec++) {
 > +    /*
 > +     * RISCV_MAXIMUM_EXTERNAL_INTERRUPTS is a valid interrupt because 0 is
 > +     * reserved for exceptions and not counted in the total number of
 > +     * interrupts
 > +     */
 > +    bsp_interrupt_set_priority(vec, 14);
 > +  }
 > +
 > +  __asm__ volatile ("fence o, i" : : : "memory");
 > +  riscv_interrupt_enable(cookie);
 > +
 > +  /* clear all mappings */
 > +  for ( uint8_t vec = 1; vec < RISCV_MAXIMUM_EXTERNAL_INTERRUPTS; vec++ ) {

Comment added to clarify.

-- 
View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1160#note_147710
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