RTEMS | risc-v: support running in s-mode (!1086)

[Kinsey Moore (@opticron)]

Kinsey Moore pushed new commits to merge request !1086
Merge request URL: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1086

* 5e9f94de...e4a02bc2 - 2 commits from branch `main`

* e84cf21c - spec/build: add RISCV_USE_S_MODE option
* d65d6c56 - riscv: support s-mode during boot
* 75572d5d - bsps/riscv: support SMP secondary processors
* f93e5462 - bsps/riscv: support s-mode timer in clock driver
* ee3f58e4 - bsps/riscv: support s-mode irq handling
* ecdabbc1 - riscv: enable s-mode in CPU port
* d10381fa - cpukit/riscv: remove s/m prefix on frame context regs
* 14f47842 - riscv/riscv: refactor clock driver
* b6fece1e - riscv/riscv: add clock driver using stimecmp
* 59f56b27 - riscv: support CPU counter in s-mode
* b2d7c024 - riscv: use software irq in tm27 with s-mode
* 3647acc5 - riscv/riscv: support s-mode IRQ handling

-- 
View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1086
You're receiving this email because of your account on gitlab.rtems.org.


-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.rtems.org/pipermail/bugs/attachments/20260226/b404c597/attachment-0001.htm>