RTEMS | risc-v: support running in s-mode (!1086)

[Kinsey Moore (@opticron)]

Kinsey Moore pushed new commits to merge request !1086
Merge request URL: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1086

* 2e08b935 - 1 commit from branch `main`

* 89187c8b - spec/build: add RISCV_USE_S_MODE option
* cedd74a6 - riscv: support s-mode during boot
* 745d4ff8 - bsps/riscv: support SMP secondary processors
* 73bcf881 - bsps/riscv: support s-mode timer in clock driver
* b9aa301c - bsps/riscv: support s-mode irq handling
* 4f6c1fbb - riscv: enable s-mode in CPU port
* 6c71e3b5 - cpukit/riscv: remove s/m prefix on frame context regs
* 2b9c95be - riscv/riscv: refactor clock driver
* a90bab45 - riscv/riscv: add clock driver using stimecmp
* 14367631 - riscv: support CPU counter in s-mode
* 49608dec - riscv: use software irq in tm27 with s-mode
* 9a4ea2cc - riscv/riscv: support s-mode IRQ handling

-- 
View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1086
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