RTEMS | risc-v: support running in s-mode (!1086)

[Gedare Bloom (@gedare)]

Gedare Bloom pushed new commits to merge request !1086
Merge request URL: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1086


* 014a84d8 - spec/build: add RISCV_USE_S_MODE option
* 03a43419 - riscv: support s-mode during boot
* 17694328 - bsps/riscv: support SMP secondary processors
* b7fe6145 - bsps/riscv: support s-mode timer in clock driver
* 2796bb52 - bsps/riscv: support s-mode irq handling
* 84bbec1f - riscv: enable s-mode in CPU port
* a560c0e2 - cpukit/riscv: remove s/m prefix on frame context regs
* 36b945af - riscv/riscv: refactor clock driver
* 95ea27b2 - riscv/riscv: add clock driver using stimecmp
* 165a0509 - riscv: support CPU counter in s-mode
* 89e115d7 - riscv: use software irq in tm27 with s-mode
* 083f3dbb - riscv/riscv: support s-mode IRQ handling

-- 
View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1086
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