RTEMS | risc-v: support running in s-mode (!1086)

[Gedare Bloom (@gedare)]

Gedare Bloom pushed new commits to merge request !1086
Merge request URL: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1086


* f36f6b4b - spec/build: add RISCV_USE_S_MODE option
* 1c2d9538 - riscv: support s-mode during boot
* b97b2aee - bsps/riscv: support SMP secondary processors
* 39314a70 - bsps/riscv: support s-mode timer in clock driver
* f7ec0bbc - bsps/riscv: support s-mode irq handling
* 5621da9d - riscv: enable s-mode in CPU port
* e5ac9822 - cpukit/riscv: remove s/m prefix on frame context regs
* 1f67bee8 - riscv/riscv: refactor clock driver
* 6a0c2258 - riscv/riscv: add clock driver using stimecmp
* b4284e9b - riscv: support CPU counter in s-mode
* 44b8414e - riscv: use software irq in tm27 with s-mode
* 1294d1b2 - riscv/riscv: support s-mode IRQ handling

-- 
View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1086
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