RTEMS | risc-v: support running in s-mode (!1086)

[Gedare Bloom (@gedare)]

Gedare Bloom pushed new commits to merge request !1086
Merge request URL: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1086

* 42df15b2...8166a413 - 2 commits from branch `main`

* 544c046e - spec/build: add RISCV_USE_S_MODE option
* ef9a573a - riscv: support s-mode during boot
* adc44444 - bsps/riscv: support SMP secondary processors
* 604344c2 - bsps/riscv: support s-mode timer in clock driver
* 8645e756 - bsps/riscv: support s-mode irq handling
* 9aa03d65 - riscv: enable s-mode in CPU port
* 8eb1c220 - cpukit/riscv: remove s/m prefix on frame context regs
* e8c686ec - riscv/riscv: refactor clock driver
* 8f769900 - riscv/riscv: add clock driver using stimecmp
* f063c0eb - riscv: support CPU counter in s-mode
* 1a715d6f - riscv: use software irq in tm27 with s-mode
* b4007e57 - riscv: avoid accessing per_cpu mtime variable in s-mode
* 99d057fe - riscv/riscv: support s-mode IRQ handling

-- 
View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1086
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