RTEMS | Draft: riscv: s-mode use SBI for timer, reset, and SMP support (!1108)

[Gedare Bloom (@gedare)]

Gedare Bloom pushed new commits to merge request !1108
Merge request URL: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1108

* ea31fe6c...e8d948eb - 2 commits from branch `main`

* a47bf110 - riscv/riscv: support using SBI timer in s-mode
* 2b2ed4ca - riscv/riscv: use shutdown SBI in s-mode
* 30564cb1 - riscv/riscv: s-mode booting with SMP
* da624d60 - riscv/riscv: remove RISCV_FATAL_CLOCK_SMP_INIT

-- 
View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1108
You're receiving this email because of your account on gitlab.rtems.org.


-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.rtems.org/pipermail/bugs/attachments/20260309/6dd50d59/attachment.htm>