RTEMS | riscv: s-mode use SBI for timer, reset, and SMP support (!1108)

[Gedare Bloom (@gedare)]

Gedare Bloom pushed new commits to merge request !1108
Merge request URL: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1108


* effb156b - riscv/riscv: s-mode booting with SMP
* d79a485f - riscv/riscv: remove RISCV_FATAL_CLOCK_SMP_INIT
* 6abd28c7 - riscv/riscv: refactor FDT helper functions

-- 
View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1108
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