RTEMS | riscv: fix spurious interrupt by using SIP_SSIP instead of SIP_STIP (!1124)

[Kinsey Moore (@opticron)]

Kinsey Moore started a new discussion on bsps/riscv/riscv/irq/irq.c: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1124#note_145729

 >  
 >    if (vector == RISCV_INTERRUPT_VECTOR_TIMER) {
 >  #ifdef RISCV_USE_S_MODE
 > -    *pending = (read_csr(sip) & SIP_STIP) != 0;
 > +  pending = (read_csr(sip) & SIP_STIP) != 0;
 >  #else
 > -    *pending = (read_csr(mip) & MIP_MTIP) != 0;
 > +  pending = (read_csr(mip) & MIP_MTIP) != 0;

Please explain what this change does.

-- 
View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1124#note_145729
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