RTEMS | riscv: fix spurious interrupt by using SIP_SSIP instead of SIP_STIP (!1124)
saksham balsane (@sak8644)
gitlab at rtems.org
Mon Mar 16 15:54:49 UTC 2026
saksham balsane commented on a discussion on bsps/riscv/riscv/irq/irq.c: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1124#note_145731
>
> if (vector == RISCV_INTERRUPT_VECTOR_TIMER) {
> #ifdef RISCV_USE_S_MODE
> - *pending = (read_csr(sip) & SIP_STIP) != 0;
> + pending = (read_csr(sip) & SIP_STIP) != 0;
> #else
> - *pending = (read_csr(mip) & MIP_MTIP) != 0;
> + pending = (read_csr(mip) & MIP_MTIP) != 0;
i would really like to apologize for this mistake of removal \*in \* pending was unintended and completely slipped passed me
--
View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1124#note_145731
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