RTEMS | riscv: fix spurious interrupt by using SIP_SSIP instead of SIP_STIP (!1124)

Tue Mar 17 20:50:04 UTC 2026

saksham balsane commented on a discussion: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1124#note_145888

for my setup i used` [riscv/rv64imac] ENABLE_TESTS = True`  to further validate the fix i created a runtime test that explicitly triggers a software interrupt using the CLINT MSIP register on the QEMU virt plaform... i have defined the MSIP  register with (`0x2000000`) i used a real ssip.. the execution took place normally before and after the interrupt which i guess confirms the software interrupt path is exercised and handled correctly 

![init.png](/uploads/95c24a9b10143f9f48c26a14b73ab7ec/init.png){width=413 height=363}

![image.png](/uploads/784bc1242f0d2e7bd14fefb994486006/image.png){width=413 height=363}

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View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1124#note_145888
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