RTEMS | riscv: fix spurious interrupt by using SIP_SSIP instead of SIP_STIP (!1124)

[Matteo Concas (@matteo.concas)]

Matteo Concas commented on a discussion: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1124#note_145935


> If there's not a test case that fails due to this, then how do we know (a) it is a valid bug, (b) the fix is correct/complete?

I made the original issue (#5522) so I will answer, I noticed this issue when running `rhilatency.exe` with an OpenSBI implementation that enabled the Sstc extension while leaving the `stimecmp` CSR to zero. The test would exit with `BSP_FATAL_SPURIOUS_INTERRUPT` as a supervisor timer interrupt would trigger while no interrupt entry for it were present.

To reproduce this issue you should only need an application that is not configured with a clock driver (`CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER`), `stimecmp` set to zero and have the application runs long enough to have the supervisor timer interrupt be triggered.

-- 
View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1124#note_145935
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