RTEMS | riscv: s-mode use SBI for timer, reset, and SMP support (!1108)

[Gedare Bloom (@gedare)]

Gedare Bloom pushed new commits to merge request !1108
Merge request URL: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1108


* 272428f1 - riscv/riscv: s-mode booting with SMP
* 685539ef - riscv/riscv: remove RISCV_FATAL_CLOCK_SMP_INIT
* d4ca5d9f - riscv/riscv: refactor FDT helper functions
* 560d5992 - riscv/riscv: fix incorrect uses of SIP_STIP for SIP_SSIP

-- 
View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1108
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