RTEMS | RISC-V: Add support for ESP32-C3 (!1160)

[Gedare Bloom (@gedare)]

Gedare Bloom started a new discussion on bsps/riscv/esp32/clock/clockdrv_systimer.c: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1160#note_147624

 > +  /* wait for updated value, typically takes 0-2 loop iterations */
 > +  while ( systimer_unit0_value_valid() == 0 ) {
 > +    ;
 > +  }
 > +
 > +  /*
 > +   * only return the low 32 bits because CPU_Counter_ticks is only 32bit and
 > +   * the configured period must be less than this
 > +   */
 > +  return SYSTIMER_REG( SYSTIMER_UNIT0_VALUE_LO_REG );
 > +}
 > +
 > +static void systimer_clock_at_tick( void )
 > +{
 > +  /* acknowledge the interrupt */
 > +  SYSTIMER_REG( SYSTIMER_INT_CLR_REG ) = SYSTIMER_TARGET0_INT_CLR ;

remove stray ` ` before `;`

-- 
View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1160#note_147624
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