RTEMS | RISC-V: Add support for ESP32-C3 (!1160)

[Kinsey Moore (@opticron)]

Kinsey Moore pushed new commits to merge request !1160
Merge request URL: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1160

* a41583c3...f76b04e1 - 2 commits from branch `main`

* 443da026 - riscv: Add support for Espressif Direct Boot
* aa120830 - riscv: Add optional section copy callback
* 3689004a - spec/bsps/riscv: Allow start section load address
* cace4261 - spec/riscv: Allow BSS to be specified independent of DATA
* 0ffb4b97 - riscv: Add support for vectored interrupt controllers
* ea01d830 - cpukit/riscv: Make use of MDT conditional on Zicsr
* 07d5d791 - riscv: Add basic ESP32-C3 BSP

-- 
View it on GitLab: https://gitlab.rtems.org/rtems/rtos/rtems/-/merge_requests/1160
You're receiving this email because of your account on gitlab.rtems.org.


-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.rtems.org/pipermail/bugs/attachments/20260325/1af8affa/attachment.htm>