SIS | gdb and riscv fixes (!16)

[Jiri Gaisler (@jirigaisler)]

Jiri Gaisler created a merge request: https://gitlab.rtems.org/rtems/tools/rtems-sis/-/merge_requests/16

Project:Branches: jirigaisler/rtems-sis:gdb to rtems/tools/rtems-sis:main
Author: Jiri Gaisler

## Summary

```
I was bringing up real Griscv hardware, and these issues came up when simulating the testbenches on sis:

func.c: go and tgo command would not start timer properly
(The run and go commands could now in fact be merged.)
   
remote.c: gdb remote stub did not detect griscv target
Griscv has a strange mix of cputype=leon3 and archtype=riscv

riscv.c: terminate sim on riscv ebreak instruction
This is to play nicely with Gaisler's NCC tool-chain
Also, announce supported IMAFDC extensions in the MISA csr.

riscv.c: send only integer registers to gdb
sis-riscv is not able to announce FPU support to gdb, so sending FPU
registers will break the remote-gdb protocol.
```

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View it on GitLab: https://gitlab.rtems.org/rtems/tools/rtems-sis/-/merge_requests/16
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