[rtems commit] bsp/genmcf548x: Enable FPU in BSP startup code

[Joel Sherrill]

Is your intent to verify this did or did not cover something up?

And if it did, to fix it

Sebastian Huber <sebh at rtems.org> wrote:

>Module:    rtems
>Branch:    master
>Commit:    6d136ed9dd9eb3a5929d18e5c7f37b5265a35f11
>Changeset: http://git.rtems.org/rtems/commit/?id=6d136ed9dd9eb3a5929d18e5c7f37b5265a35f11
>
>Author:    Sebastian Huber <sebastian.huber at embedded-brains.de>
>Date:      Fri Apr 20 14:03:39 2012 +0200
>
>bsp/genmcf548x: Enable FPU in BSP startup code
>
>---
>
> .../lib/libbsp/m68k/genmcf548x/startup/bspstart.c  |   18 +++++-------------
> 1 files changed, 5 insertions(+), 13 deletions(-)
>
>diff --git a/c/src/lib/libbsp/m68k/genmcf548x/startup/bspstart.c b/c/src/lib/libbsp/m68k/genmcf548x/startup/bspstart.c
>index 743ad4c..9de5d56 100644
>--- a/c/src/lib/libbsp/m68k/genmcf548x/startup/bspstart.c
>+++ b/c/src/lib/libbsp/m68k/genmcf548x/startup/bspstart.c
>@@ -70,8 +70,10 @@ extern char WorkAreaBase [];
> #define m68k_set_acr3(_acr3) __asm__ volatile ("movec %0,#0x0007" : : "d" (_acr3))
> 
> /*
>- * Set initial cacr mode, mainly enables branch/intruction/data cache and
>- * switch off FPU.
>+ * Set initial CACR mode, mainly enables branch/instruction/data cache.  The
>+ * FPU must be switched on in the BSP startup code since the
>+ * _Thread_Start_multitasking() will restore the floating-point context of the
>+ * initialization task if necessary.
>  */
> static const uint32_t BSP_CACR_INIT = MCF548X_CACR_DEC /* enable data cache */
>   | MCF548X_CACR_BEC /* enable branch cache */
>@@ -80,8 +82,7 @@ static const uint32_t BSP_CACR_INIT = MCF548X_CACR_DEC /* enable data cache */
>       /* set data cache mode to write-through */
>   | MCF548X_CACR_DESB /* enable data store buffer */
>   | MCF548X_CACR_DDSP /* data access only in supv. mode */
>-  | MCF548X_CACR_IDSP /* instr. access only in supv. mode */
>-  | MCF548X_CACR_DF; /* disable FPU */
>+  | MCF548X_CACR_IDSP; /* instr. access only in supv. mode */
> 
> /*
>  * CACR maintenance functions
>@@ -273,15 +274,6 @@ void bsp_start( void )
>   /* Initialize CACR shadow register */
>   _CPU_cacr_shadow = BSP_CACR_INIT;
> 
>-  /* Switch on FPU in CACR shadow register if necessary */
>-  if ((Configuration_POSIX_API.number_of_initialization_threads > 0) ||
>-      ((Configuration_RTEMS_API.number_of_initialization_tasks > 0) &&
>-       (Configuration_RTEMS_API.User_initialization_tasks_table
>-	->attribute_set & RTEMS_FLOATING_POINT) != 0)
>-      ) {
>-    _CPU_cacr_shadow &= ~MCF548X_CACR_DF;
>-  }
>-
>   /*
>    * Load the shadow variable of CACR with initial mode and write it to the
>    * CACR.  Interrupts are still disabled, so there is no need for surrounding
>
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