Interrupt gate in x86
claudiodcsilva at gmail.com
Mon Jul 2 09:10:19 UTC 2012
I am not knowledgeable about the x86 interrupt management but it seems
to me that the ISR_Handler enables processor interrupts and changes
the PIC mask. So higher priority interrupts can still occur.
You need the _ISR_Nest_level variable to keep track of the interrupt
nesting of the current interrupt. Only the outer interrupt can change
from the tasks' stack to the ISR's stack and call _Thread_Dispatch.
On Mon, Jul 2, 2012 at 5:28 AM, Fered <a_Fered at yahoo.com> wrote:
> My question is about Interrupt Descriptor Table (IDT) initialization. RTEMS
> initializes all descriptors as "Interrupt Gate". If you are familiar with x86
> architecture, it have 3 gates for execution of handlers:
> Interrupt gate, trap gate and task gate.
> If we use "interrupt gate", processor clears IF flag, then all maskable
> interrupts masked. If interrupts masked, then we have no interrupt at the
> middle of execution of the handler. Then nested interrupting is disabled.
> I saw "irq_asm.S" and as I said, "_ISR_Nest_level" increases before
> dispatching of Interrupt handler. But I think if we use "Interrupt Gate" then
> "_ISR_Nest_level" doesn't exceed one.
> My question is "Is it true what I said about the variable?".
> you wrote:
>> Have a look here wherever you've installed RTEMS --
>> -- dc
>> On Sun, Jul 1, 2012 at 7:26 AM, Fered <a_Fered at yahoo.com> wrote:
>> > Nobody can help me?!
>> > Fered wrote:
>> >> Hi;
>> >> In the following file:
>> >> c/src/lib/libbsp/i386/shared/irq/idt.c
>> >> in the following function:
>> >> create_interrupt_gate_descriptor ()
>> >> interrupt descriptor type, set to 0xe. It mean "Interrupt Gate" has been
>> >> used. Interrupt gate clears IF flag then prevents nested interrupts. But
>> >> I
>> >> think nested interrupt handling implemented in RTEMS, according to usage
>> >> of
>> >> "_ISR_Nest_level" variable.
>> >> Can anyone tell me how nesting implemented in interrupt handler of RTEMS?
>> >> Thanks.
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