ARM RTEMS SMP Support

[Joel Sherrill]

You just threw down the gauntlet to Xi Yang!! Time to
merge. :)

On 2/13/2013 12:02 PM, Claus, Ric wrote:
> SMP is not available for ARM?  That's a big issue for me.  What's involved to provide that support?
Compared to writing a BSP from scratch, not much. :)

You can look at either the pc386 or leon3 BSPs and associated
ports for an idea of how much code is architecture
and BSP specific.

Or even better.. help us merge the GSOC project by Xi Yang.

http://www.rtems.com/ml/rtems-users/2012/august/msg00084.html
has a github link. I suspect there may be some BSP or CPU model
variation between his work and yours.

Our atomic code is based off that in FreeBSD. So this would be the
starting point for the atomic.h support.

http://svnweb.freebsd.org/base/head/sys/arm/include/atomic.h?view=log&pathrev=151334

--joel
>
> Ric
>
> ________________________________________
> From: rtems-devel-bounces at rtems.org [rtems-devel-bounces at rtems.org] On Behalf Of Joel Sherrill [joel.sherrill at OARcorp.com]
> Sent: Wednesday, February 13, 2013 8:42 AM
> To: yangwei weiyang
> Cc: RTEMS Devel
> Subject: Re: [rtems commit] tests: atomic support for RTEMS. Uniprocessor tests for atomic ops.
>
> On 2/13/2013 10:28 AM, yangwei weiyang wrote:
>> OK i am studying how to implement a common ISR_Disable and ISR_Enable
>> ops to simulate atomic ops. But it is just for the UP architectures,
>> for SMP architectures which are not supported by atomic now this will
>> not be suitable.
> That's OK. The only architectures we currently support SMP on are
> x86 and SPARC (only for LEON3).  Beyond powerpc and arm, I think
> it is unlikely we will have SMP.
>
> In general terms, if the CPU doesn't have atomic instructions
> to implement these with, then it is very unlikely to ever show
> up in an SMP configuration.  This makes the ISR disable/enable
> implementation suitable for UP.
>
> My biggest concerns is more general. I envision two common
> scenarios within a single architecture:
>
> + certain cpu models or architecture revisions have atomic
>      instructions and some don't. But this is defined in the
>     architecture and can be handled in cpukit. ISR disable/enable
>      in some cases, real atomic in others.
> + Similar case but CPU models have pulled instructions from
>      architectural revisions "above" them. The instruction is
>      there but not part of the real architectural revision the CPU
>      model is based upon.
>
> The isr disable/enable implementation may need to be available
> all the time as a fallback.
>
> --joel


-- 
Joel Sherrill, Ph.D.             Director of Research & Development
joel.sherrill at OARcorp.com        On-Line Applications Research
Ask me about RTEMS: a free RTOS  Huntsville AL 35805
Support Available                (256) 722-9985

-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://lists.rtems.org/pipermail/devel/attachments/20130213/081efa12/attachment-0001.html>