ARM RTEMS SMP Support

[Xi Yang]

On 19 February 2013 06:41, Joel Sherrill <joel.sherrill at oarcorp.com> wrote:
> On 2/18/2013 2:21 AM, Xi Yang wrote:
>>
>> On 14 February 2013 10:39, Joel Sherrill <joel.sherrill at oarcorp.com>
>> wrote:
>>>
>>> Xi
>>>
>>> Can you post the URL for your project? And a general bit
>>> on the status and target. That way if someone wants to help,
>>> everything will be right here.
>>
>> I am doing a research project for my PhD, which is using M3 cores to
>> do garbage collection for the JVM. The JVM is running on big A9 cores.
>> I don't have a URL for that. I will post the paper and code URL to the
>> mailing list after it is accepted.
>>
> Very cool!
>
> But I actually meant a link for the ARM SMP work you did so anyone
> on the list can review, comment, pitch in.  We all would love to see it
> merged so having more eyes on it would help get it ready and merged
> sooner.

Sorry, I misunderstand your question. Here is the link
https://github.com/yangxi/omap4m3

Regards.

>
> hint.. I am hoping someone will step up and do this... hint..
>
>> Regards.
>>>
>>> --joel
>>>
>>> On 2/13/2013 4:56 PM, Xi Yang wrote:
>>>>
>>>> Hi Joel,
>>>>
>>>> On 14 February 2013 05:37, Joel Sherrill <joel.sherrill at oarcorp.com>
>>>> wrote:
>>>>>
>>>>> You just threw down the gauntlet to Xi Yang!! Time to
>>>>> merge. :)
>>>>>
>>>>> On 2/13/2013 12:02 PM, Claus, Ric wrote:
>>>>>
>>>>> SMP is not available for ARM?  That's a big issue for me.  What's
>>>>> involved
>>>>> to provide that support?
>>>>>
>>>>> Compared to writing a BSP from scratch, not much. :)
>>>>>
>>>>> You can look at either the pc386 or leon3 BSPs and associated
>>>>> ports for an idea of how much code is architecture
>>>>> and BSP specific.
>>>>>
>>>>> Or even better.. help us merge the GSOC project by Xi Yang.
>>>>
>>>> Sorry, Joel. I was too busy to clean the code. I will try my best to
>>>> submit the patches as soon as possible.
>>>>
>>>> By the way, I am doing a research project which is using RTEMS as the
>>>> kernel for the small M3 ARM cores.
>>>>
>>>>
>>>> Regards.
>>>>
>>>>> http://www.rtems.com/ml/rtems-users/2012/august/msg00084.html
>>>>> has a github link. I suspect there may be some BSP or CPU model
>>>>> variation between his work and yours.
>>>>>
>>>>> Our atomic code is based off that in FreeBSD. So this would be the
>>>>> starting point for the atomic.h support.
>>>>>
>>>>>
>>>>>
>>>>> http://svnweb.freebsd.org/base/head/sys/arm/include/atomic.h?view=log&pathrev=151334
>>>>>
>>>>> --joel
>>>>>
>>>>> Ric
>>>>>
>>>>> ________________________________________
>>>>> From: rtems-devel-bounces at rtems.org [rtems-devel-bounces at rtems.org] On
>>>>> Behalf Of Joel Sherrill [joel.sherrill at OARcorp.com]
>>>>> Sent: Wednesday, February 13, 2013 8:42 AM
>>>>> To: yangwei weiyang
>>>>> Cc: RTEMS Devel
>>>>> Subject: Re: [rtems commit] tests: atomic support for RTEMS.
>>>>> Uniprocessor
>>>>> tests for atomic ops.
>>>>>
>>>>> On 2/13/2013 10:28 AM, yangwei weiyang wrote:
>>>>>
>>>>> OK i am studying how to implement a common ISR_Disable and ISR_Enable
>>>>> ops to simulate atomic ops. But it is just for the UP architectures,
>>>>> for SMP architectures which are not supported by atomic now this will
>>>>> not be suitable.
>>>>>
>>>>> That's OK. The only architectures we currently support SMP on are
>>>>> x86 and SPARC (only for LEON3).  Beyond powerpc and arm, I think
>>>>> it is unlikely we will have SMP.
>>>>>
>>>>> In general terms, if the CPU doesn't have atomic instructions
>>>>> to implement these with, then it is very unlikely to ever show
>>>>> up in an SMP configuration.  This makes the ISR disable/enable
>>>>> implementation suitable for UP.
>>>>>
>>>>> My biggest concerns is more general. I envision two common
>>>>> scenarios within a single architecture:
>>>>>
>>>>> + certain cpu models or architecture revisions have atomic
>>>>>       instructions and some don't. But this is defined in the
>>>>>      architecture and can be handled in cpukit. ISR disable/enable
>>>>>       in some cases, real atomic in others.
>>>>> + Similar case but CPU models have pulled instructions from
>>>>>       architectural revisions "above" them. The instruction is
>>>>>       there but not part of the real architectural revision the CPU
>>>>>       model is based upon.
>>>>>
>>>>> The isr disable/enable implementation may need to be available
>>>>> all the time as a fallback.
>>>>>
>>>>> --joel
>>>>>
>>>>>
>>>>>
>>>>> --
>>>>> Joel Sherrill, Ph.D.             Director of Research & Development
>>>>> joel.sherrill at OARcorp.com        On-Line Applications Research
>>>>> Ask me about RTEMS: a free RTOS  Huntsville AL 35805
>>>>> Support Available                (256) 722-9985
>>>
>>>
>>>
>>> --
>>> Joel Sherrill, Ph.D.             Director of Research & Development
>>> joel.sherrill at OARcorp.com        On-Line Applications Research
>>> Ask me about RTEMS: a free RTOS  Huntsville AL 35805
>>> Support Available                (256) 722-9985
>>>
>
>
> --
> Joel Sherrill, Ph.D.             Director of Research & Development
> joel.sherrill at OARcorp.com        On-Line Applications Research
> Ask me about RTEMS: a free RTOS  Huntsville AL 35805
> Support Available                (256) 722-9985
>