[PATCH 2/2] smp: Delete _ISR_Disable_on_this_core(), etc.
Sebastian Huber
sebastian.huber at embedded-brains.de
Fri Jul 26 14:41:22 UTC 2013
Delete _ISR_Enable_on_this_core(), _ISR_Flash_on_this_core(),
_ISR_SMP_Disable(), _ISR_SMP_Enable(), _ISR_SMP_Flash().
The ISR disable/enable interface has no parameter to pass a specific
object. Thus it is only possible to implement a single global lock
object with this interface. Using the ISR disable/enable as the giant
lock on SMP configurations is not feasible.
Potentially blocking resource obtain sequences protected by the thread
dispatch disable level are subdivided into smaller ISR disabled critical
sections. This works since on single processor configurations there is
only one thread of execution that can block. On SMP this is different
(image a mutex obtained concurrently by different threads on different
processors).
The thread dispatch disable level is currently used as the giant lock.
There is not need to complicate things with this unused interface.
---
cpukit/score/include/rtems/score/isrlevel.h | 139 +++++--------------------
cpukit/score/src/isrsmp.c | 28 +-----
cpukit/score/src/smp.c | 2 +-
cpukit/score/src/threaddispatchdisablelevel.c | 8 +-
4 files changed, 33 insertions(+), 144 deletions(-)
diff --git a/cpukit/score/include/rtems/score/isrlevel.h b/cpukit/score/include/rtems/score/isrlevel.h
index 32263db..35d3d03 100644
--- a/cpukit/score/include/rtems/score/isrlevel.h
+++ b/cpukit/score/include/rtems/score/isrlevel.h
@@ -41,40 +41,46 @@ extern "C" {
typedef uint32_t ISR_Level;
/**
- * @brief Disable interrupts on this core.
+ * @brief Disables interrupts on this processor.
*
- * This routine disables all interrupts so that a critical section
- * of code can be executing without being interrupted.
+ * This macro disables all interrupts on this processor so that a critical
+ * section of code is protected from concurrent access by interrupts of this
+ * processor. Disabling of interrupts disables thread dispatching on the
+ * processor as well.
*
- * @retval The argument @a _level will contain the previous interrupt
- * mask level.
+ * On SMP configurations other processors can enter such sections if not
+ * protected by other means.
+ *
+ * @param[out] _level The argument @a _level will contain the previous
+ * interrupt mask level.
*/
-#define _ISR_Disable_on_this_core( _level ) \
+#define _ISR_Disable( _level ) \
do { \
_CPU_ISR_Disable( _level ); \
RTEMS_COMPILER_MEMORY_BARRIER(); \
} while (0)
/**
- * @brief Enable interrupts on this core.
+ * @brief Enables interrupts on this processor.
*
- * This routine enables interrupts to the previous interrupt mask
- * LEVEL. It is used at the end of a critical section of code to
- * enable interrupts so they can be processed again.
+ * This macro restores the interrupt status on the processor with the
+ * interrupt level value obtained by _ISR_Disable(). It is used at the end of
+ * a critical section of code to enable interrupts so they can be processed
+ * again.
*
- * @param[in] _level contains the interrupt level mask level
- * previously returned by @ref _ISR_Disable_on_this_core.
+ * @param[in] _level The interrupt level previously obtained by
+ * _ISR_Disable().
*/
-#define _ISR_Enable_on_this_core( _level ) \
+#define _ISR_Enable( _level ) \
do { \
RTEMS_COMPILER_MEMORY_BARRIER(); \
_CPU_ISR_Enable( _level ); \
} while (0)
/**
- * @brief Temporarily enable interrupts on this core.
+ * @brief Temporarily enables interrupts on this processor.
*
- * This routine temporarily enables interrupts to the previous
+ * This macro temporarily enables interrupts to the previous
* interrupt mask level and then disables all interrupts so that
* the caller can continue into the second part of a critical
* section.
@@ -87,113 +93,16 @@ typedef uint32_t ISR_Level;
* must be selected with care to ensure that the critical section
* properly protects itself.
*
- * @param[in] _level contains the interrupt level mask level
- * previously returned by @ref _ISR_Disable_on_this_core.
+ * @param[in] _level The interrupt level previously obtained by
+ * _ISR_Disable().
*/
-#define _ISR_Flash_on_this_core( _level ) \
+#define _ISR_Flash( _level ) \
do { \
RTEMS_COMPILER_MEMORY_BARRIER(); \
_CPU_ISR_Flash( _level ); \
RTEMS_COMPILER_MEMORY_BARRIER(); \
} while (0)
-#if defined( RTEMS_SMP )
-
-/**
- * @brief Enter interrupt critical section on SMP system.
- *
- * This method is used to enter an interrupt critical section that
- * is honored across all cores in an SMP system.
- *
- * @retval This method returns the previous interrupt mask level.
- */
-ISR_Level _ISR_SMP_Disable(void);
-
-/**
- * @brief Exit interrupt critical section on SMP system.
- *
- * This method is used to exit an interrupt critical section that
- * is honored across all cores in an SMP system.
- *
- * @param[in] level contains the interrupt level mask level
- * previously returned by @ref _ISR_SMP_Disable.
- */
-void _ISR_SMP_Enable(ISR_Level level);
-
-/**
- * @brief Temporarily exit interrupt critical section on SMP system.
- *
- * This method is used to temporarily exit an interrupt critical section
- * that is honored across all cores in an SMP system.
- *
- * @param[in] level contains the interrupt level mask level
- * previously returned by @ref _ISR_SMP_Disable.
- */
-void _ISR_SMP_Flash(ISR_Level level);
-
-#endif /* defined( RTEMS_SMP ) */
-
-/**
- * @brief Enter interrupt disable critical section.
- *
- * This routine enters an interrupt disable critical section. When
- * in an SMP configuration, this involves obtaining a spinlock to ensure
- * that only one core is inside an interrupt disable critical section.
- * When on a single core system, this only involves disabling local
- * CPU interrupts.
- *
- * @retval The argument @a _level will contain the previous interrupt
- * mask level.
- */
-#if defined( RTEMS_SMP )
- #define _ISR_Disable( _level ) \
- _level = _ISR_SMP_Disable();
-#else
- #define _ISR_Disable( _level ) \
- _ISR_Disable_on_this_core( _level );
-#endif
-
-/**
- * @brief Exits interrupt disable critical section.
- *
- * This routine exits an interrupt disable critical section. When
- * in an SMP configuration, this involves releasing a spinlock.
- * When on a single core system, this only involves disabling local
- * CPU interrupts.
- *
- * @retval The argument @a _level will contain the previous interrupt
- * mask level.
- */
-#if defined( RTEMS_SMP )
- #define _ISR_Enable( _level ) \
- _ISR_SMP_Enable( _level );
-#else
- #define _ISR_Enable( _level ) \
- _ISR_Enable_on_this_core( _level );
-#endif
-
-/**
- * @brief Temporarily exit interrupt disable critical section.
- *
- * This routine is used to temporarily enable interrupts
- * during a long critical section. It is used in long sections of
- * critical code when a point is reached at which interrupts can
- * be temporarily enabled. Deciding where to flash interrupts
- * in a long critical section is often difficult and the point
- * must be selected with care to ensure that the critical section
- * properly protects itself.
- *
- * @retval The argument @a _level will contain the previous interrupt
- * mask level.
- */
-#if defined( RTEMS_SMP )
- #define _ISR_Flash( _level ) \
- _ISR_SMP_Flash( _level );
-#else
- #define _ISR_Flash( _level ) \
- _ISR_Flash_on_this_core( _level );
-#endif
-
/**
* @brief Return current interrupt level.
*
diff --git a/cpukit/score/src/isrsmp.c b/cpukit/score/src/isrsmp.c
index 7725c30..2f292b0 100644
--- a/cpukit/score/src/isrsmp.c
+++ b/cpukit/score/src/isrsmp.c
@@ -24,33 +24,13 @@
#include <rtems/score/threaddispatch.h>
#include <rtems/score/smp.h>
-ISR_Level _ISR_SMP_Disable(void)
-{
- ISR_Level level;
-
- _ISR_Disable_on_this_core( level );
- return level;
-}
-
-void _ISR_SMP_Enable(ISR_Level level)
-{
- _ISR_Enable_on_this_core( level );
-}
-
-void _ISR_SMP_Flash(ISR_Level level)
-{
- ISR_Level ignored;
-
- _ISR_SMP_Enable( level );
- ignored = _ISR_SMP_Disable();
-}
-
int _ISR_SMP_Enter(void)
{
uint32_t isr_nest_level;
ISR_Level level;
- _ISR_Disable_on_this_core( level );
+ /* FIXME: Where is the corresponding _ISR_Enable()? */
+ _ISR_Disable( level );
isr_nest_level = _ISR_Nest_level++;
@@ -66,7 +46,7 @@ int _ISR_SMP_Exit(void)
retval = 0;
- _ISR_Disable_on_this_core( level );
+ _ISR_Disable( level );
_ISR_Nest_level--;
@@ -88,7 +68,7 @@ int _ISR_SMP_Exit(void)
retval = 0;
#endif
- _ISR_Enable_on_this_core( level );
+ _ISR_Enable( level );
_Thread_Dispatch_decrement_disable_level();
diff --git a/cpukit/score/src/smp.c b/cpukit/score/src/smp.c
index 6c580a4..5b299b4 100644
--- a/cpukit/score/src/smp.c
+++ b/cpukit/score/src/smp.c
@@ -98,7 +98,7 @@ void rtems_smp_process_interrupt( void )
#endif
if ( ( message & RTEMS_BSP_SMP_SHUTDOWN ) != 0 ) {
- _ISR_Disable_on_this_core( level );
+ _ISR_Disable( level );
_Thread_Dispatch_set_disable_level( 0 );
diff --git a/cpukit/score/src/threaddispatchdisablelevel.c b/cpukit/score/src/threaddispatchdisablelevel.c
index f1c971e..816959a 100644
--- a/cpukit/score/src/threaddispatchdisablelevel.c
+++ b/cpukit/score/src/threaddispatchdisablelevel.c
@@ -49,7 +49,7 @@ uint32_t _Thread_Dispatch_increment_disable_level( void )
uint32_t self_cpu;
uint32_t disable_level;
- _ISR_Disable_on_this_core( isr_level );
+ _ISR_Disable( isr_level );
/*
* We must obtain the processor ID after interrupts are disabled since a
@@ -69,7 +69,7 @@ uint32_t _Thread_Dispatch_increment_disable_level( void )
++disable_level;
_Thread_Dispatch_disable_level = disable_level;
- _ISR_Enable_on_this_core( isr_level );
+ _ISR_Enable( isr_level );
return disable_level;
}
@@ -81,7 +81,7 @@ uint32_t _Thread_Dispatch_decrement_disable_level( void )
ISR_Level isr_level;
uint32_t disable_level;
- _ISR_Disable_on_this_core( isr_level );
+ _ISR_Disable( isr_level );
disable_level = _Thread_Dispatch_disable_level;
--disable_level;
@@ -93,7 +93,7 @@ uint32_t _Thread_Dispatch_decrement_disable_level( void )
_SMP_lock_Release( &level_lock->lock );
}
- _ISR_Enable_on_this_core( isr_level );
+ _ISR_Enable( isr_level );
return disable_level;
}
--
1.7.7
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