RTEMS_malta board support
gedare at rtems.org
Tue Jun 25 18:53:15 UTC 2013
On Tue, Jun 25, 2013 at 2:44 PM, Joel Sherrill
<Joel.Sherrill at oarcorp.com> wrote:
> The bsp was built to match the configuration in qemu.
> At the risk of repeating myself, the Malta board manual clearly states that there are multiple variants with multiple system controllers. Plus the CPU model can vary. The details of your hardware neg to be verified against what variant qemu supports.
In that case, the BSP for the eval board should be implemented as a
BSP variant. I don't see any examples in mips, but the arm bsp
families have a lot of examples of BSP variants, see for example
> MIPS uses the upper few bits of an address to specify user or kernel space.. Cached or not.. The BSP needs kernel space.
OK thanks for the info. Should the virtual addresses all be in the
kernel space then? If so, it seems likely the requested address is
> The vector is two ASCII printable characters but that may be a coincidence. :-)
> Gedare Bloom <gedare at rtems.org> wrote:
> Caveat: I am not familiar with RTEMS's MIPS support or Malta BSP.
> On Tue, Jun 25, 2013 at 7:20 AM, CHINTHA MOL C.S. <chintha308 at gmail.com> wrote:
>> Hi all,
>> I would like to port RTEMS to malta mips evaluation board.
>> I successfully built RTEMS 4.10.99 with malta BSP.
>> I need to load the generated hello.ralf to malta board with YAMON
> Is there a simulator you can first run the BSP on? Maybe someone with
> experiences with this BSP can chime in.
>> I edited the MIPS Malta linker script .
>> RAM base is changed from 0x80000000 to 0x800c0000. and section start from
>> 0x80010000 to 0x80100000.
>> I converted the hello.ralf file to srec format using mips-retms4.11-objcopy
>> and successfully loaded it via tftp. But while running it, exception in TLB
>> occures. the error log is given below.
> "EPC = 0x80100050" tells you the address of the instruction that
> caused the exception. You should see what function that is in, and
> maybe you can figure out the line of source code too from inspecting
> the disassembly (e.g. mips-rtems4.11-objdump -d hello.ralf >
> BadVAddr = 0x00004234 looks suspicious considering your memory address
> space appears to be defined with the upper bit set.
>> How can i successfully run this rtems-application (hello.ralf) in malta
>> Compilation time = Dec 7 2006 19:00:35
>> Board type/revision = 0x02 (Malta) / 0x00
>> Core board type/revision = 0x01 (CoreLV) / 0x01
>> System controller/revision = Galileo / GT_64120A-B-2
>> FPGA revision = 0x0001
>> MAC address = 00.d0.a0.00.05.e9
>> Board S/N = 0000001245
>> PCI bus frequency = 33.33 MHz
>> Processor Company ID/options = 0x01 (MIPS Technologies, Inc.) / 0x80
>> Processor ID/revision = 0x90 (MIPS 4KEc) / 0x68
>> Endianness = Little
>> CPU/Bus frequency = 240 MHz / 80 MHz
>> Flash memory size = 4 MByte
>> SDRAM size = 128 MByte
>> First free SDRAM address = 0x800b7350
>> YAMON> load
>> About to load tftp://10.1.125.98/hello.srec
>> Press Ctrl-C to break
>> Start = 0x80100024, range = (0x80100000,0x801348a7), format = SREC
>> YAMON> go 0x80100024
>> * Exception (user) : TLB (store) *
>> BadVAddr = 0x00004234 Cause = 0xd080800c
>> Compare = 0xced7cdbf Config = 0x80250483
>> Config1 = 0xbe994c8e Config2 = 0x80000000
>> Config3 = 0x00000020 Context = 0xdf800020
>> Count = 0xc21f9d1d DEPC = 0xdf5f1e43
>> Debug = 0x0e017c3f EBase = 0x80000000
>> EPC = 0x80100050 EntryHi = 0x000040ff
>> EntryLo0 = 0x01f7f555 EntryLo1 = 0x01bf36d7
>> ErrorEPC = 0xbfc00380 HWREna = 0x00000000
>> Index = 0x80000014 IntCtl = 0xe0000000
>> PRId = 0x80019068 PageGrain = 0x00000000
>> PageMask = 0x19ffe000 Random = 0x0000001e
>> SRSCtl = 0x00000000 SRSMap = 0x00000000
>> Status = 0x00002c02 WatchHi = 0x00000000
>> WatchLo = 0x00000000 Wired = 0x00000000
>> Hi = 0x00000000 Lo = 0x80100020
>> $ 0(zr):0x00000000 $ 8(t0):0x00000000 $16(s0):0x00000000
>> $ 1(at):0x00000000 $ 9(t1):0x00000000 $17(s1):0x00000000
>> $ 2(v0):0x00000000 $10(t2):0x00000000 $18(s2):0x00000000
>> $ 3(v1):0x00000000 $11(t3):0x00000000 $19(s3):0x00000000
>> $ 4(a0):0x00000001 $12(t4):0x00000000 $20(s4):0x00000000
>> $ 5(a1):0x800ad268 $13(t5):0x00000000 $21(s5):0x00000000
>> $ 6(a2):0x8006dccc $14(t6):0x00000000 $22(s6):0x00000000
>> $ 7(a3):0x08000000 $15(t7):0x00000000 $23(s7):0x00000000
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