SMP cache synchronisation

Daniel Hellstrom daniel at
Thu Oct 24 13:49:56 UTC 2013

On 10/24/2013 03:41 PM, Sebastian Huber wrote:
> On 2013-10-24 15:15, Daniel Hellstrom wrote:
>>  From code analysis and testing SMP on LEON I can see that when installing a
>> trap handler the cache is not invalidated correctly on other CPUs then the CPU
>> installing the new trap handler. In the single-core case this is correct, but
>> for SMP we must flush all CPUs caches. I think this is a platform independent
>> problem for all self-modifying code. On the LEON SMP we normally don't see this
>> since since the bad traps that are installed are never taken.
>> My suggestion is that we use a IPI to signal to other CPUs to invalidate their
>> instruction cache, and CPU requesting such a remote CPU(s) flush should wait
>> until all remote CPUs signal that their cache has been invalidated. The cache
>> library could be extended to support SMP. Perhaps is should not be a platform
>> independednt IPI solution, but rather a libcpu/BSP specific implementation for
>> implementing cache flush on another CPU?
>> What do think about this issue?
> The LEON3 has only an operation that invalidates the complete cache, so here a simple inter-processor event can be used.  On other platforms you have to perform invalidation by set/way or address.  
> Here you have to deal with more than one bit of information which makes things a bit more complicated.
Of course, the cache manager should be able to invalidate regions which is mapped down to the whole cache on a LEON. I agree. Note that the LEON behaviour in this regard may not always be limited to 
the whole cache, it would be a pity to limit it to the first LEON cache model ;)

> It seems we need a low-level message queue with a broadcast to all processors feature.  We likely need also low-level barrier operations.



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