[PATCH 1/8] Fixed stm32f4 linker script flash location
Chris Nott
chrisn at vl.com.au
Fri Apr 4 21:07:16 UTC 2014
Signed-off-by: Chris Nott <chrisn at vl.com.au>
---
c/src/lib/libbsp/arm/stm32f4/startup/linkcmds.stm32f4 | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/c/src/lib/libbsp/arm/stm32f4/startup/linkcmds.stm32f4 b/c/src/lib/libbsp/arm/stm32f4/startup/linkcmds.stm32f4
index 8219505..1ff6d02 100644
--- a/c/src/lib/libbsp/arm/stm32f4/startup/linkcmds.stm32f4
+++ b/c/src/lib/libbsp/arm/stm32f4/startup/linkcmds.stm32f4
@@ -1,6 +1,6 @@
MEMORY {
RAM_INT : ORIGIN = 0x20000000, LENGTH = 128k
- ROM_INT : ORIGIN = 0x00000000, LENGTH = 1M
+ ROM_INT : ORIGIN = 0x08000000, LENGTH = 1M
}
REGION_ALIAS ("REGION_START", ROM_INT);
--
1.8.4.2
>From 1a8fb7a83838071f88b8d2df4432b12e48c16da3 Mon Sep 17 00:00:00 2001
From: Chris Nott <chrisn at vl.com.au>
Date: Wed, 29 Jan 2014 10:46:18 -0800
Subject: [PATCH 3/8] Added STM32F4 headers, and PLL configuration functions
---
c/src/lib/libbsp/arm/stm32f4/Makefile.am | 5 +
c/src/lib/libbsp/arm/stm32f4/include/rcc.h | 2 +
c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h | 35 +++-
.../libbsp/arm/stm32f4/include/stm32f4xxxx_exti.h | 64 +++++++
.../libbsp/arm/stm32f4/include/stm32f4xxxx_flash.h | 83 +++++++++
.../libbsp/arm/stm32f4/include/stm32f4xxxx_pwr.h | 47 +++++
.../libbsp/arm/stm32f4/include/stm32f4xxxx_rcc.h | 124 +++++++++++++
.../arm/stm32f4/include/stm32f4xxxx_syscfg.h | 108 +++++++++++
.../libbsp/arm/stm32f4/include/stm32f4xxxx_tim.h | 206 +++++++++++++++++++++
c/src/lib/libbsp/arm/stm32f4/preinstall.am | 20 ++
c/src/lib/libbsp/arm/stm32f4/startup/bspstart.c | 2 +
c/src/lib/libbsp/arm/stm32f4/startup/rcc.c | 145 +++++++++++++++
12 files changed, 840 insertions(+), 1 deletion(-)
mode change 100644 => 100755 c/src/lib/libbsp/arm/stm32f4/include/rcc.h
mode change 100644 => 100755 c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
create mode 100755 c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_exti.h
create mode 100755 c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_flash.h
create mode 100755 c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_pwr.h
mode change 100644 => 100755 c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_rcc.h
create mode 100755 c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_syscfg.h
create mode 100755 c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_tim.h
mode change 100644 => 100755 c/src/lib/libbsp/arm/stm32f4/startup/bspstart.c
mode change 100644 => 100755 c/src/lib/libbsp/arm/stm32f4/startup/rcc.c
diff --git a/c/src/lib/libbsp/arm/stm32f4/Makefile.am b/c/src/lib/libbsp/arm/stm32f4/Makefile.am
index 8bdaa5e..4ea4334 100644
--- a/c/src/lib/libbsp/arm/stm32f4/Makefile.am
+++ b/c/src/lib/libbsp/arm/stm32f4/Makefile.am
@@ -50,8 +50,13 @@ include_bsp_HEADERS += include/stm32f4.h
include_bsp_HEADERS += include/stm32f10xxx_gpio.h
include_bsp_HEADERS += include/stm32f10xxx_rcc.h
include_bsp_HEADERS += include/stm32f10xxx_exti.h
+include_bsp_HEADERS += include/stm32f4xxxx_exti.h
include_bsp_HEADERS += include/stm32f4xxxx_gpio.h
include_bsp_HEADERS += include/stm32f4xxxx_rcc.h
+include_bsp_HEADERS += include/stm32f4xxxx_pwr.h
+include_bsp_HEADERS += include/stm32f4xxxx_syscfg.h
+include_bsp_HEADERS += include/stm32f4xxxx_tim.h
+include_bsp_HEADERS += include/stm32f4xxxx_flash.h
include_bsp_HEADERS += include/stm32_i2c.h
include_bsp_HEADERS += include/i2c.h
include_bsp_HEADERS += include/stm32_usart.h
diff --git a/c/src/lib/libbsp/arm/stm32f4/include/rcc.h b/c/src/lib/libbsp/arm/stm32f4/include/rcc.h
old mode 100644
new mode 100755
index c105470..3e44c0a
--- a/c/src/lib/libbsp/arm/stm32f4/include/rcc.h
+++ b/c/src/lib/libbsp/arm/stm32f4/include/rcc.h
@@ -146,6 +146,8 @@ typedef enum {
#endif /* STM32F4_FAMILY_F10XXX */
} stm32f4_rcc_index;
+void stm32f4_rcc_init (void);
+
void stm32f4_rcc_reset(stm32f4_rcc_index index);
void stm32f4_rcc_set_reset(stm32f4_rcc_index index, bool set);
diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
old mode 100644
new mode 100755
index 9059d18..8272a2d
--- a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
+++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
@@ -22,11 +22,16 @@
#ifdef STM32F4_FAMILY_F4XXXX
+#define STM32F4_APB1_BASE (STM32F4_BASE + 0x40000000)
+#define STM32F4_APB2_BASE (STM32F4_BASE + 0x40010000)
+#define STM32F4_AHB1_BASE (STM32F4_BASE + 0x40020000)
+#define STM32F4_AHB2_BASE (STM32F4_BASE + 0x50000000)
+
#include <bsp/stm32f4xxxx_gpio.h>
#define STM32F4_GPIO(i) ((volatile stm32f4_gpio *) (STM32F4_BASE + 0x40020000) + (i))
#include <bsp/stm32f4xxxx_rcc.h>
-#define STM32F4_RCC ((volatile stm32f4_rcc *) (STM32F4_BASE + 0x40023800))
+#define STM32F4_RCC ((volatile stm32f4_rcc *) (STM32F4_AHB1_BASE + 0x3800))
#include <bsp/stm32_i2c.h>
#define STM32F4_I2C3 ((volatile stm32f4_i2c *) (STM32F4_BASE + 0x40005C00))
@@ -41,6 +46,34 @@
#define STM32F4_USART_5 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40005000))
#define STM32F4_USART_6 ((volatile stm32f4_usart *) (STM32F4_BASE + 0x40011400))
+#include <bsp/stm32f4xxxx_pwr.h>
+#define STM32F4_PWR ((volatile stm32f4_pwr *) (STM32F4_APB1_BASE + 0x7000))
+
+#include <bsp/stm32f4xxxx_exti.h>
+#define STM32F4_EXTI ((volatile stm32f4_exti *) (STM32F4_APB2_BASE + 0x3c00))
+
+#include <bsp/stm32f4xxxx_syscfg.h>
+#define STM32F4_SYSCFG ((volatile stm32f4_syscfg *) (STM32F4_APB2_BASE + 0x3800))
+
+#include <bsp/stm32f4xxxx_flash.h>
+#define STM32F4_FLASH ((volatile stm32f4_flash *) (STM32F4_AHB1_BASE + 0x3c00))
+
+#include <bsp/stm32f4xxxx_tim.h>
+#define STM32F4_TIM1 ((volatile stm32f4_tim *) (STM32F4_APB2_BASE + 0x0000))
+#define STM32F4_TIM2 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x0000))
+#define STM32F4_TIM3 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x0400))
+#define STM32F4_TIM4 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x0800))
+#define STM32F4_TIM5 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x0c00))
+#define STM32F4_TIM6 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x1000))
+#define STM32F4_TIM7 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x1400))
+#define STM32F4_TIM8 ((volatile stm32f4_tim *) (STM32F4_APB2_BASE + 0x0400))
+#define STM32F4_TIM9 ((volatile stm32f4_tim *) (STM32F4_APB2_BASE + 0x4000))
+#define STM32F4_TIM10 ((volatile stm32f4_tim *) (STM32F4_APB2_BASE + 0x4400))
+#define STM32F4_TIM11 ((volatile stm32f4_tim *) (STM32F4_APB2_BASE + 0x4800))
+#define STM32F4_TIM12 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x1800))
+#define STM32F4_TIM13 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x1c00))
+#define STM32F4_TIM14 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x2000))
+
#endif /* STM32F4_FAMILY_F4XXXX */
#ifdef STM32F4_FAMILY_F10XXX
diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_exti.h b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_exti.h
new file mode 100755
index 0000000..feff2c6
--- /dev/null
+++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_exti.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2013 Chris Nott. All rights reserved.
+ *
+ * Virtual Logic
+ * 21-25 King St.
+ * Rockdale NSW 2216
+ * Australia
+ * <rtems at vl.com.au>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_EXTI_H
+#define LIBBSP_ARM_STM32F4_STM32F4XXXX_EXTI_H
+
+#include <bsp/utility.h>
+
+#define EXTI_PORTA 0
+#define EXTI_PORTB 1
+#define EXTI_PORTC 2
+#define EXTI_PORTD 3
+#define EXTI_PORTE 4
+#define EXTI_PORTF 5
+#define EXTI_PORTG 6
+#define EXTI_PORTH 7
+#define EXTI_PORTI 8
+
+#define STM32F4_EXTI_LINE22 BSP_BIT32(21)
+#define STM32F4_EXTI_LINE21 BSP_BIT32(21)
+#define STM32F4_EXTI_LINE20 BSP_BIT32(20)
+#define STM32F4_EXTI_LINE19 BSP_BIT32(19)
+#define STM32F4_EXTI_LINE18 BSP_BIT32(18)
+#define STM32F4_EXTI_LINE17 BSP_BIT32(17)
+#define STM32F4_EXTI_LINE16 BSP_BIT32(16)
+#define STM32F4_EXTI_LINE15 BSP_BIT32(15)
+#define STM32F4_EXTI_LINE14 BSP_BIT32(14)
+#define STM32F4_EXTI_LINE13 BSP_BIT32(13)
+#define STM32F4_EXTI_LINE12 BSP_BIT32(12)
+#define STM32F4_EXTI_LINE11 BSP_BIT32(11)
+#define STM32F4_EXTI_LINE10 BSP_BIT32(10)
+#define STM32F4_EXTI_LINE9 BSP_BIT32(9)
+#define STM32F4_EXTI_LINE8 BSP_BIT32(8)
+#define STM32F4_EXTI_LINE7 BSP_BIT32(7)
+#define STM32F4_EXTI_LINE6 BSP_BIT32(6)
+#define STM32F4_EXTI_LINE5 BSP_BIT32(5)
+#define STM32F4_EXTI_LINE4 BSP_BIT32(4)
+#define STM32F4_EXTI_LINE3 BSP_BIT32(3)
+#define STM32F4_EXTI_LINE2 BSP_BIT32(2)
+#define STM32F4_EXTI_LINE1 BSP_BIT32(1)
+#define STM32F4_EXTI_LINE0 BSP_BIT32(0)
+
+struct stm32f4_exti_s {
+ uint32_t imr; // Interrupt mask
+ uint32_t emr; // Event mask
+ uint32_t rtsr; // Rising trigger selection
+ uint32_t ftsr; // Falling trigger selection
+ uint32_t swier; // Software interrupt event
+ uint32_t pr; // Pending
+} __attribute__ ((packed));
+typedef struct stm32f4_exti_s stm32f4_exti;
+
+#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_EXTI_H */
diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_flash.h b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_flash.h
new file mode 100755
index 0000000..5e643bd
--- /dev/null
+++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_flash.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2013 Chris Nott. All rights reserved.
+ *
+ * Virtual Logic
+ * 21-25 King St.
+ * Rockdale NSW 2216
+ * Australia
+ * <rtems at vl.com.au>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_FLASH_H
+#define LIBBSP_ARM_STM32F4_STM32F4XXXX_FLASH_H
+
+#include <bsp/utility.h>
+
+struct stm32f4_flash_s {
+
+ uint32_t acr; // Access and control register
+#define STM32F4_FLASH_ACR_DCRST BSP_BIT32(12) // Data cache reset
+#define STM32F4_FLASH_ACR_ICRST BSP_BIT32(11) // Instruction cache reset
+#define STM32F4_FLASH_ACR_DCEN BSP_BIT32(10) // Data cache enable
+#define STM32F4_FLASH_ACR_ICEN BSP_BIT32(9) // Instruction cache enable
+#define STM32F4_FLASH_ACR_PRFTEN BSP_BIT32(8) // Prefetch enable
+#define STM32F4_FLASH_ACR_LATENCY(val) BSP_FLD32(val, 0, 2) // Flash access latency
+#define STM32F4_FLASH_ACR_LATENCY_GET(reg) BSP_FLD32GET(reg, 0, 2)
+#define STM32F4_FLASH_ACR_LATENCY_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2)
+
+ uint32_t keyr; // Key register
+#define STM32F4_FLASH_KEYR_KEY1 0x45670123
+#define STM32F4_FLASH_KEYR_KEY2 0xCDEF89AB
+
+ uint32_t optkeyr; // Option key register
+#define STM32F4_FLASH_OPTKEYR_OPTKEY1 0x08192A3B
+#define STM32F4_FLASH_OPTKEYR_OPTKEY2 0x4C5D6E7F
+
+ uint32_t sr; // Status register
+#define STM32F4_FLASH_SR_BSY BSP_BIT32(16) // Busy
+#define STM32F4_FLASH_SR_PGSERR BSP_BIT32(7) // Programming sequence error
+#define STM32F4_FLASH_SR_PGPERR BSP_BIT32(6) // Programming parallelism error
+#define STM32F4_FLASH_SR_PGAERR BSP_BIT32(5) // Programming alignment error
+#define STM32F4_FLASH_SR_WRPERR BSP_BIT32(4) // Write protection error
+#define STM32F4_FLASH_SR_OPERR BSP_BIT32(1) // Operation error
+#define STM32F4_FLASH_SR_EOP BSP_BIT32(0) // End of operation
+
+ uint32_t cr; // Control register
+#define STM32F4_FLASH_CR_LOCK BSP_BIT32(31) // Lock
+#define STM32F4_FLASH_CR_ERRIE BSP_BIT32(25) // Error interrupt enable
+#define STM32F4_FLASH_CR_EOPIE BSP_BIT32(24) // End of operation interrupt enable
+#define STM32F4_FLASH_CR_STRT BSP_BIT32(16) // Start
+#define STM32F4_FLASH_CR_PSIZE(val) BSP_FLD32(val, 8, 9) // Program size
+#define STM32F4_FLASH_CR_PSIZE_GET(reg) BSP_FLD32GET(reg, 8, 9)
+#define STM32F4_FLASH_CR_PSIZE_SET(reg, val) BSP_FLD32SET(reg, val, 8, 9)
+#define STM32F4_FLASH_CR_SNB BSP_FLD32(val, 3, 6) // Sector number
+#define STM32F4_FLASH_CR_SNB_GET(reg) BSP_FLD32GET(reg, 3, 6)
+#define STM32F4_FLASH_CR_SNB_SET(reg, val) BSP_FLD32SET(reg, val, 3, 6)
+#define STM32F4_FLASH_CR_MER BSP_BIT32(2) // Mass erase
+#define STM32F4_FLASH_CR_SER BSP_BIT32(1) // Sector erase
+#define STM32F4_FLASH_CR_PG BSP_BIT32(0) // Programming
+
+ uint32_t optcr; // Option control register
+#define STM32F4_FLASH_OPTCR_NWRP(val) BSP_FLD32(val, 16, 27) // Not write protect
+#define STM32F4_FLASH_OPTCR_NWRP_GET(reg) BSP_FLD32GET(reg, 16, 27)
+#define STM32F4_FLASH_OPTCR_NWRP_SET(reg, val) BSP_FLD32SET(reg, val, 16, 27)
+#define STM32F4_FLASH_OPTCR_RDP(val) BSP_FLD32(val, 8, 15) // Read protect
+#define STM32F4_FLASH_OPTCR_RDP_GET(reg) BSP_FLD32GET(reg, 8, 15)
+#define STM32F4_FLASH_OPTCR_RDP_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
+#define STM32F4_FLASH_OPTCR_USER(val) BSP_FLD32(val, 5, 7) // User option bytes
+#define STM32F4_FLASH_OPTCR_USER_GET(reg) BSP_FLD32GET(reg, 5, 7)
+#define STM32F4_FLASH_OPTCR_USER_SET(reg, val) BSP_FLD32SET(reg, val, 5, 7)
+#define STM32F4_FLASH_OPTCR_BOR_LEVEL(val) BSP_FLD32(val, 2, 3) // BOR reset level
+#define STM32F4_FLASH_OPTCR_BOR_LEVEL_GET(reg) BSP_FLD32GET(reg, 2, 3)
+#define STM32F4_FLASH_OPTCR_BOR_LEVEL_SET(reg, val) BSP_FLD32SET(reg, val, 2, 3)
+#define STM32F4_FLASH_CR_OPTSTRT BSP_BIT32(1) // Option start
+#define STM32F4_FLASH_CR_OPTLOCK BSP_BIT32(0) // Option lock
+
+} __attribute__ ((packed));
+typedef struct stm32f4_flash_s stm32f4_flash;
+
+#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_FLASH_H */
diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_pwr.h b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_pwr.h
new file mode 100755
index 0000000..092a400
--- /dev/null
+++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_pwr.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2013 Chris Nott. All rights reserved.
+ *
+ * Virtual Logic
+ * 21-25 King St.
+ * Rockdale NSW 2216
+ * Australia
+ * <rtems at vl.com.au>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_PWR_H
+#define LIBBSP_ARM_STM32F4_STM32F4XXXX_PWR_H
+
+#include <bsp/utility.h>
+
+struct stm32f4_pwr_s {
+
+ uint32_t cr; // Control register
+#define STM32F4_PWR_CR_VOS BSP_BIT32(14) // Regulator scaling output selection
+#define STM32F4_PWR_CR_FPDS BSP_BIT32(9) // Flash power-down in stop mode
+#define STM32F4_PWR_CR_DBP BSP_BIT32(8) // Disable backup domain write protection
+#define STM32F4_PWR_CR_PLS BSP_FLD32(val, 5, 7) // PVD level selection
+#define STM32F4_PWR_CR_PLS_GET(reg) BSP_FLD32GET(reg, 5, 7)
+#define STM32F4_PWR_CR_PLS_SET(reg, val) BSP_FLD32SET(reg, val, 5, 7)
+#define STM32F4_PWR_CR_PVDE BSP_BIT32(4) // Power voltage detector enable
+#define STM32F4_PWR_CR_CSBF BSP_BIT32(3) // Clear standby flag
+#define STM32F4_PWR_CR_CWUF BSP_BIT32(2) // Clear wakeup flag
+#define STM32F4_PWR_CR_PDDS BSP_BIT32(1) // Power-down deepsleep
+#define STM32F4_PWR_CR_LPDS BSP_BIT32(0) // Low-power deepsleep
+
+ uint32_t csr; // Control / status register
+#define STM32F4_PWR_CSR_VOSRDY BSP_BIT32(14) // Regulator voltage scaling output selection ready bit
+#define STM32F4_PWR_CSR_BRE BSP_BIT32(9) // Backup domain regulator enable
+#define STM32F4_PWR_CSR_EWUP BSP_BIT32(8) // Enable WKUP pin
+#define STM32F4_PWR_CSR_BRR BSP_BIT32(3) // Backup regulator ready
+#define STM32F4_PWR_CSR_PVDO BSP_BIT32(2) // PVD output
+#define STM32F4_PWR_CSR_SBF BSP_BIT32(1) // Standby flag
+#define STM32F4_PWR_CSR_WUF BSP_BIT32(0) // Wakeup flag
+
+} __attribute__ ((packed));
+typedef struct stm32f4_pwr_s stm32f4_pwr;
+
+#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_PWR_H */
diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_rcc.h b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_rcc.h
old mode 100644
new mode 100755
index 61e8d5f..71f987c
--- a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_rcc.h
+++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_rcc.h
@@ -19,26 +19,150 @@
typedef struct {
uint32_t cr;
+#define STM32F4_RCC_CR_PLLI2SRDY BSP_BIT32(27) // PLLI2S clock ready flag
+#define STM32F4_RCC_CR_PLLI2SON BSP_BIT32(26) // PLLI2S enable
+#define STM32F4_RCC_CR_PLLRDY BSP_BIT32(25) // Main PLL clock ready flag
+#define STM32F4_RCC_CR_PLLON BSP_BIT32(24) // Main PLL enable
+#define STM32F4_RCC_CR_CSSON BSP_BIT32(19) // Clock security system enable
+#define STM32F4_RCC_CR_HSEBYP BSP_BIT32(18) // HSE clock bypass
+#define STM32F4_RCC_CR_HSERDY BSP_BIT32(17) // HSE clock ready flag
+#define STM32F4_RCC_CR_HSEON BSP_BIT32(16) // HSE clock enable
+#define STM32F4_RCC_CR_HSIRDY BSP_BIT32(1) // HSI clock ready flag
+#define STM32F4_RCC_CR_HSION BSP_BIT32(0) // HSI clock enable
+
uint32_t pllcfgr;
+#define STM32F4_RCC_PLLCFGR_PLLQ(val) BSP_FLD32(val, 24, 27)
+#define STM32F4_RCC_PLLCFGR_PLLQ_GET(reg) BSP_FLD32GET(reg, 24, 27)
+#define STM32F4_RCC_PLLCFGR_PLLQ_SET(reg, val) BSP_FLD32SET(reg, val, 24, 27)
+#define STM32F4_RCC_PLLCFGR_SRC BSP_BIT32(22) // PLL entry clock source
+#define STM32F4_RCC_PLLCFGR_SRC_HSE STM32F4_RCC_PLLCFGR_SRC
+#define STM32F4_RCC_PLLCFGR_SRC_HSI 0
+#define STM32F4_RCC_PLLCFGR_PLLP(val) BSP_FLD32(val, 16, 17)
+#define STM32F4_RCC_PLLCFGR_PLLP_GET(reg) BSP_FLD32GET(reg, 16, 17)
+#define STM32F4_RCC_PLLCFGR_PLLP_SET(reg, val) BSP_FLD32SET(reg, val, 16, 17)
+#define STM32F4_RCC_PLLCFGR_PLLP_2 STM32F4_RCC_PLLCFGR_PLLP(0)
+#define STM32F4_RCC_PLLCFGR_PLLP_4 STM32F4_RCC_PLLCFGR_PLLP(1)
+#define STM32F4_RCC_PLLCFGR_PLLP_6 STM32F4_RCC_PLLCFGR_PLLP(2)
+#define STM32F4_RCC_PLLCFGR_PLLP_8 STM32F4_RCC_PLLCFGR_PLLP(3)
+#define STM32F4_RCC_PLLCFGR_PLLN(val) BSP_FLD32(val, 6, 14)
+#define STM32F4_RCC_PLLCFGR_PLLN_GET(reg) BSP_FLD32GET(reg, 6, 14)
+#define STM32F4_RCC_PLLCFGR_PLLN_SET(reg, val) BSP_FLD32SET(reg, val, 6, 14)
+#define STM32F4_RCC_PLLCFGR_PLLM(val) BSP_FLD32(val, 0, 5)
+#define STM32F4_RCC_PLLCFGR_PLLM_GET(reg) BSP_FLD32GET(reg, 0, 5)
+#define STM32F4_RCC_PLLCFGR_PLLM_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5)
+
uint32_t cfgr;
+#define STM32F4_RCC_CFGR_MCO2(val) BSP_FLD32(val, 30, 31) // Microcontroller clock output 2
+#define STM32F4_RCC_CFGR_MCO2_GET(reg) BSP_FLD32GET(reg, 30, 31)
+#define STM32F4_RCC_CFGR_MCO2_SET(reg, val) BSP_FLD32SET(reg, val, 30, 31)
+#define STM32F4_RCC_CFGR_MCO2_SYSCLK STM32F4_RCC_CFGR_MCO2(0)
+#define STM32F4_RCC_CFGR_MCO2_PLLI2S STM32F4_RCC_CFGR_MCO2(1)
+#define STM32F4_RCC_CFGR_MCO2_HSE STM32F4_RCC_CFGR_MCO2(2)
+#define STM32F4_RCC_CFGR_MCO2_PLL STM32F4_RCC_CFGR_MCO2(3)
+#define STM32F4_RCC_CFGR_MCO2_PRE(val) BSP_FLD32(val, 27, 29) // MCO2 prescalar
+#define STM32F4_RCC_CFGR_MCO2_PRE_GET(reg) BSP_FLD32GET(reg, 27, 29)
+#define STM32F4_RCC_CFGR_MCO2_PRE_SET(reg, val) BSP_FLD32SET(reg, val, 27, 29)
+#define STM32F4_RCC_CFGR_MCO2_DIV1 STM32F4_RCC_CFGR_MCO2_PRE(0)
+#define STM32F4_RCC_CFGR_MCO2_DIV2 STM32F4_RCC_CFGR_MCO2_PRE(4)
+#define STM32F4_RCC_CFGR_MCO2_DIV3 STM32F4_RCC_CFGR_MCO2_PRE(5)
+#define STM32F4_RCC_CFGR_MCO2_DIV4 STM32F4_RCC_CFGR_MCO2_PRE(6)
+#define STM32F4_RCC_CFGR_MCO2_DIV5 STM32F4_RCC_CFGR_MCO2_PRE(7)
+#define STM32F4_RCC_CFGR_MCO1_PRE(val) BSP_FLD32(val, 24, 26) // MCO1 prescalar
+#define STM32F4_RCC_CFGR_MCO1_PRE_GET(reg) BSP_FLD32GET(reg, 24, 26)
+#define STM32F4_RCC_CFGR_MCO1_PRE_SET(reg, val) BSP_FLD32SET(reg, val, 24, 26)
+#define STM32F4_RCC_CFGR_MCO1_DIV1 STM32F4_RCC_CFGR_MCO1_PRE(0)
+#define STM32F4_RCC_CFGR_MCO1_DIV2 STM32F4_RCC_CFGR_MCO1_PRE(4)
+#define STM32F4_RCC_CFGR_MCO1_DIV3 STM32F4_RCC_CFGR_MCO1_PRE(5)
+#define STM32F4_RCC_CFGR_MCO1_DIV4 STM32F4_RCC_CFGR_MCO1_PRE(6)
+#define STM32F4_RCC_CFGR_MCO1_DIV5 STM32F4_RCC_CFGR_MCO1_PRE(7)
+#define STM32F4_RCC_CFGR_I2SSCR BSP_BIT32(23) // I2S clock selection
+#define STM32F4_RCC_CFGR_MCO1(val) BSP_FLD32(val, 21, 22) // Microcontroller clock output 1
+#define STM32F4_RCC_CFGR_MCO1_GET(reg) BSP_FLD32GET(reg, 21, 22)
+#define STM32F4_RCC_CFGR_MCO1_SET(reg, val) BSP_FLD32SET(reg, val, 21, 22)
+#define STM32F4_RCC_CFGR_MCO1_HSI STM32F4_RCC_CFGR_MCO1(0)
+#define STM32F4_RCC_CFGR_MCO1_LSE STM32F4_RCC_CFGR_MCO1(1)
+#define STM32F4_RCC_CFGR_MCO1_HSE STM32F4_RCC_CFGR_MCO1(2)
+#define STM32F4_RCC_CFGR_MCO1_PLL STM32F4_RCC_CFGR_MCO1(3)
+#define STM32F4_RCC_CFGR_RTCPRE(val) BSP_FLD32(val, 16, 20) // HSE division factor for RTC clock
+#define STM32F4_RCC_CFGR_RTCPRE_GET(reg) BSP_FLD32GET(reg, 16, 20)
+#define STM32F4_RCC_CFGR_RTCPRE_SET(reg, val) BSP_FLD32SET(reg, val, 16, 20)
+#define STM32F4_RCC_CFGR_PPRE2(val) BSP_FLD32(val, 13, 15) // APB high-speed prescalar (APB2)
+#define STM32F4_RCC_CFGR_PPRE2_GET(reg) BSP_FLD32GET(reg, 13, 15)
+#define STM32F4_RCC_CFGR_PPRE2_SET(reg, val) BSP_FLD32SET(reg, val, 13, 15)
+#define STM32F4_RCC_CFGR_PPRE2_DIV1 STM32F4_RCC_CFGR_PPRE2(0)
+#define STM32F4_RCC_CFGR_PPRE2_DIV2 STM32F4_RCC_CFGR_PPRE2(4)
+#define STM32F4_RCC_CFGR_PPRE2_DIV4 STM32F4_RCC_CFGR_PPRE2(5)
+#define STM32F4_RCC_CFGR_PPRE2_DIV8 STM32F4_RCC_CFGR_PPRE2(6)
+#define STM32F4_RCC_CFGR_PPRE2_DIV16 STM32F4_RCC_CFGR_PPRE2(7)
+#define STM32F4_RCC_CFGR_PPRE1(val) BSP_FLD32(val, 10, 12) // APB low-speed prescalar (APB1)
+#define STM32F4_RCC_CFGR_PPRE1_GET(reg) BSP_FLD32GET(reg, 10, 12)
+#define STM32F4_RCC_CFGR_PPRE1_SET(reg, val) BSP_FLD32SET(reg, val, 10, 12)
+#define STM32F4_RCC_CFGR_PPRE1_DIV1 STM32F4_RCC_CFGR_PPRE1(0)
+#define STM32F4_RCC_CFGR_PPRE1_DIV2 STM32F4_RCC_CFGR_PPRE1(4)
+#define STM32F4_RCC_CFGR_PPRE1_DIV4 STM32F4_RCC_CFGR_PPRE1(5)
+#define STM32F4_RCC_CFGR_PPRE1_DIV8 STM32F4_RCC_CFGR_PPRE1(6)
+#define STM32F4_RCC_CFGR_PPRE1_DIV16 STM32F4_RCC_CFGR_PPRE1(7)
+#define STM32F4_RCC_CFGR_HPRE(val) BSP_FLD32(val, 4, 15) // AHB prescalar
+#define STM32F4_RCC_CFGR_HPRE_GET(reg) BSP_FLD32GET(reg, 4, 7)
+#define STM32F4_RCC_CFGR_HPRE_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7)
+#define STM32F4_RCC_CFGR_HPRE_DIV1 STM32F4_RCC_CFGR_HPRE(0)
+#define STM32F4_RCC_CFGR_HPRE_DIV2 STM32F4_RCC_CFGR_HPRE(8)
+#define STM32F4_RCC_CFGR_HPRE_DIV4 STM32F4_RCC_CFGR_HPRE(9)
+#define STM32F4_RCC_CFGR_HPRE_DIV8 STM32F4_RCC_CFGR_HPRE(10)
+#define STM32F4_RCC_CFGR_HPRE_DIV16 STM32F4_RCC_CFGR_HPRE(11)
+#define STM32F4_RCC_CFGR_HPRE_DIV64 STM32F4_RCC_CFGR_HPRE(12)
+#define STM32F4_RCC_CFGR_HPRE_DIV128 STM32F4_RCC_CFGR_HPRE(13)
+#define STM32F4_RCC_CFGR_HPRE_DIV256 STM32F4_RCC_CFGR_HPRE(14)
+#define STM32F4_RCC_CFGR_HPRE_DIV512 STM32F4_RCC_CFGR_HPRE(15)
+#define STM32F4_RCC_CFGR_SWS(val) BSP_FLD32(val, 2, 3) // System clock switch status
+#define STM32F4_RCC_CFGR_SWS_GET(reg) BSP_FLD32GET(reg, 2, 3)
+#define STM32F4_RCC_CFGR_SWS_SET(reg, val) BSP_FLD32SET(reg, val, 2, 3)
+#define STM32F4_RCC_CFGR_SWS_HSI STM32F4_RCC_CFGR_SWS(0)
+#define STM32F4_RCC_CFGR_SWS_HSE STM32F4_RCC_CFGR_SWS(1)
+#define STM32F4_RCC_CFGR_SWS_PLL STM32F4_RCC_CFGR_SWS(2)
+#define STM32F4_RCC_CFGR_SW(val) BSP_FLD32(val, 0, 1) // System clock switch
+#define STM32F4_RCC_CFGR_SW_GET(reg) BSP_FLD32GET(reg, 0, 1)
+#define STM32F4_RCC_CFGR_SW_SET(reg, val) BSP_FLD32SET(reg, val, 0, 1)
+#define STM32F4_RCC_CFGR_SW_HSI STM32F4_RCC_CFGR_SW(0)
+#define STM32F4_RCC_CFGR_SW_HSE STM32F4_RCC_CFGR_SW(1)
+#define STM32F4_RCC_CFGR_SW_PLL STM32F4_RCC_CFGR_SW(2)
+
uint32_t cir;
+
uint32_t ahbrstr [3];
+
uint32_t reserved_1c;
+
uint32_t apbrstr [2];
+
uint32_t reserved_28 [2];
+
uint32_t ahbenr [3];
+
uint32_t reserved_3c;
+
uint32_t apbenr [2];
+
uint32_t reserved_48 [2];
+
uint32_t ahblpenr [3];
+
uint32_t reserved_5c;
+
uint32_t apblpenr [2];
+
uint32_t reserved_68 [2];
+
uint32_t bdcr;
+
uint32_t csr;
+
uint32_t reserved_78 [2];
+
uint32_t sscgr;
+
uint32_t plli2scfgr;
+
} stm32f4_rcc;
#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_RCC_H */
diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_syscfg.h b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_syscfg.h
new file mode 100755
index 0000000..613d924
--- /dev/null
+++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_syscfg.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2013 Chris Nott. All rights reserved.
+ *
+ * Virtual Logic
+ * 21-25 King St.
+ * Rockdale NSW 2216
+ * Australia
+ * <rtems at vl.com.au>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_SYSCFG_H
+#define LIBBSP_ARM_STM32F4_STM32F4XXXX_SYSCFG_H
+
+#include <bsp/utility.h>
+
+#define EXTI_PORTA 0
+#define EXTI_PORTB 1
+#define EXTI_PORTC 2
+#define EXTI_PORTD 3
+#define EXTI_PORTE 4
+#define EXTI_PORTF 5
+#define EXTI_PORTG 6
+#define EXTI_PORTH 7
+#define EXTI_PORTI 8
+
+struct stm32f4_syscfg_s {
+ uint32_t memrmp; // Memory remap
+#define STM32F4_SYSCFG_MEM_MODE(val) BSP_FLD32(val, 0, 1)
+#define STM32F4_SYSCFG_MEM_MODE_GET(reg) BSP_FLD32GET(reg, 0, 1)
+#define STM32F4_SYSCFG_MEM_MODE_SET(reg, val) BSP_FLD32SET(reg, val, 0, 1)
+ uint32_t pmc; // Peripheral mode configuration
+#define STM32F4_SYSCFG_RMII_SEL BSP_BIT32(23)
+ uint32_t exticr[4]; // External interrupt configuration
+#define STM32F4_SYSCFG_EXTI0_IDX 0
+#define STM32F4_SYSCFG_EXTI0(val) BSP_FLD32(val, 0, 3)
+#define STM32F4_SYSCFG_EXTI0_GET(reg) BSP_FLD32GET(reg, 0, 3)
+#define STM32F4_SYSCFG_EXTI0_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
+#define STM32F4_SYSCFG_EXTI1_IDX 0
+#define STM32F4_SYSCFG_EXTI1(val) BSP_FLD32(val, 4, 7)
+#define STM32F4_SYSCFG_EXTI1_GET(reg) BSP_FLD32GET(reg, 4, 7)
+#define STM32F4_SYSCFG_EXTI1_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7)
+#define STM32F4_SYSCFG_EXTI2_IDX 0
+#define STM32F4_SYSCFG_EXTI2(val) BSP_FLD32(val, 8, 11)
+#define STM32F4_SYSCFG_EXTI2_GET(reg) BSP_FLD32GET(reg, 8, 11)
+#define STM32F4_SYSCFG_EXTI2_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11)
+#define STM32F4_SYSCFG_EXTI3_IDX 0
+#define STM32F4_SYSCFG_EXTI3(val) BSP_FLD32(val, 12, 15)
+#define STM32F4_SYSCFG_EXTI3_GET(reg) BSP_FLD32GET(reg, 12, 15)
+#define STM32F4_SYSCFG_EXTI3_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15)
+#define STM32F4_SYSCFG_EXTI4_IDX 1
+#define STM32F4_SYSCFG_EXTI4(val) BSP_FLD32(val, 0, 3)
+#define STM32F4_SYSCFG_EXTI4_GET(reg) BSP_FLD32GET(reg, 0, 3)
+#define STM32F4_SYSCFG_EXTI4_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
+#define STM32F4_SYSCFG_EXTI5_IDX 1
+#define STM32F4_SYSCFG_EXTI5(val) BSP_FLD32(val, 4, 7)
+#define STM32F4_SYSCFG_EXTI5_GET(reg) BSP_FLD32GET(reg, 4, 7)
+#define STM32F4_SYSCFG_EXTI5_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7)
+#define STM32F4_SYSCFG_EXTI6_IDX 1
+#define STM32F4_SYSCFG_EXTI6(val) BSP_FLD32(val, 8, 11)
+#define STM32F4_SYSCFG_EXTI6_GET(reg) BSP_FLD32GET(reg, 8, 11)
+#define STM32F4_SYSCFG_EXTI6_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11)
+#define STM32F4_SYSCFG_EXTI7_IDX 1
+#define STM32F4_SYSCFG_EXTI7(val) BSP_FLD32(val, 12, 15)
+#define STM32F4_SYSCFG_EXTI7_GET(reg) BSP_FLD32GET(reg, 12, 15)
+#define STM32F4_SYSCFG_EXTI7_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15)
+#define STM32F4_SYSCFG_EXTI8_IDX 2
+#define STM32F4_SYSCFG_EXTI8(val) BSP_FLD32(val, 0, 3)
+#define STM32F4_SYSCFG_EXTI8_GET(reg) BSP_FLD32GET(reg, 0, 3)
+#define STM32F4_SYSCFG_EXTI8_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
+#define STM32F4_SYSCFG_EXTI9_IDX 2
+#define STM32F4_SYSCFG_EXTI9(val) BSP_FLD32(val, 4, 7)
+#define STM32F4_SYSCFG_EXTI9_GET(reg) BSP_FLD32GET(reg, 4, 7)
+#define STM32F4_SYSCFG_EXTI9_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7)
+#define STM32F4_SYSCFG_EXTI10_IDX 2
+#define STM32F4_SYSCFG_EXTI10(val) BSP_FLD32(val, 8, 11)
+#define STM32F4_SYSCFG_EXTI10_GET(reg) BSP_FLD32GET(reg, 8, 11)
+#define STM32F4_SYSCFG_EXTI10_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11)
+#define STM32F4_SYSCFG_EXTI11_IDX 2
+#define STM32F4_SYSCFG_EXTI11(val) BSP_FLD32(val, 12, 15)
+#define STM32F4_SYSCFG_EXTI11_GET(reg) BSP_FLD32GET(reg, 12, 15)
+#define STM32F4_SYSCFG_EXTI11_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15)
+#define STM32F4_SYSCFG_EXTI12_IDX 3
+#define STM32F4_SYSCFG_EXTI12(val) BSP_FLD32(val, 0, 3)
+#define STM32F4_SYSCFG_EXTI12_GET(reg) BSP_FLD32GET(reg, 0, 3)
+#define STM32F4_SYSCFG_EXTI12_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
+#define STM32F4_SYSCFG_EXTI13_IDX 3
+#define STM32F4_SYSCFG_EXTI13(val) BSP_FLD32(val, 4, 7)
+#define STM32F4_SYSCFG_EXTI13_GET(reg) BSP_FLD32GET(reg, 4, 7)
+#define STM32F4_SYSCFG_EXTI13_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7)
+#define STM32F4_SYSCFG_EXTI14_IDX 3
+#define STM32F4_SYSCFG_EXTI14(val) BSP_FLD32(val, 8, 11)
+#define STM32F4_SYSCFG_EXTI14_GET(reg) BSP_FLD32GET(reg, 8, 11)
+#define STM32F4_SYSCFG_EXTI14_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11)
+#define STM32F4_SYSCFG_EXTI15_IDX 3
+#define STM32F4_SYSCFG_EXTI15(val) BSP_FLD32(val, 12, 15)
+#define STM32F4_SYSCFG_EXTI15_GET(reg) BSP_FLD32GET(reg, 12, 15)
+#define STM32F4_SYSCFG_EXTI15_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15)
+ uint32_t cmpcr; // Compensation cell control register
+#define STM32F4_SYSCFG_CMPCR_READY BSP_BIT32(8)
+#define STM32F4_SYSCFG_CMPCR_PD BSP_BIT32(0)
+} __attribute__ ((packed));
+typedef struct stm32f4_syscfg_s stm32f4_syscfg;
+
+#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_SYSCFG_H */
diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_tim.h b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_tim.h
new file mode 100755
index 0000000..aa89976
--- /dev/null
+++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_tim.h
@@ -0,0 +1,206 @@
+/*
+ * Copyright (c) 2013 Chris Nott. All rights reserved.
+ *
+ * Virtual Logic
+ * 21-25 King St.
+ * Rockdale NSW 2216
+ * Australia
+ * <rtems at vl.com.au>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_TIM_H
+#define LIBBSP_ARM_STM32F4_STM32F4XXXX_TIM_H
+
+#include <bsp/utility.h>
+
+struct stm32f4_tim_s {
+ uint16_t cr1; // Control register 1
+#define STM32F4_TIMER_CR1_CKD_DIV 0x0300
+#define STM32F4_TIMER_CR1_CKD_DIV1 0x0000
+#define STM32F4_TIMER_CR1_CKD_DIV2 0x0100
+#define STM32F4_TIMER_CR1_CKD_DIV3 0x0200
+#define STM32F4_TIMER_CR1_ARPE BSP_BIT16(7)
+#define STM32F4_TIMER_CR1_CMS 0x0060
+#define STM32F4_TIMER_CR1_CMS_EDGE 0x0000
+#define STM32F4_TIMER_CR1_CMS_CENTER1 0x0020
+#define STM32F4_TIMER_CR1_CMS_CENTER2 0x0040
+#define STM32F4_TIMER_CR1_CMS_CENTER3 0x0060
+#define STM32F4_TIMER_CR1_DIR BSP_BIT16(4)
+#define STM32F4_TIMER_CR1_DIR_UP 0x0000
+#define STM32F4_TIMER_CR1_DIR_DOWN 0x0010
+#define STM32F4_TIMER_CR1_DIR_OPM 0x0008
+#define STM32F4_TIMER_CR1_DIR_OPM_CONT 0x0000
+#define STM32F4_TIMER_CR1_DIR_OPM_STOP 0x0008
+#define STM32F4_TIMER_CR1_DIR_URS 0x0004
+#define STM32F4_TIMER_CR1_DIR_UDIS 0x0002
+#define STM32F4_TIMER_CR1_DIR_UDIS_EN 0x0000
+#define STM32F4_TIMER_CR1_DIR_UDIS_DIS 0x0002
+#define STM32F4_TIMER_CR1_CEN 0x0001
+ uint16_t reserved_02;
+ uint16_t cr2; // Control register 2
+ uint16_t reserved_06;
+ uint16_t smcr; // Slave mode control register
+ uint16_t reserved_0a;
+ uint16_t dier; // DMA / interrupt enable register
+#define STM32F4_TIMER_DIER_TDE BSP_BIT16(14) // Trigger DMA request enable
+#define STM32F4_TIMER_DIER_CC4DE BSP_BIT16(12) // Capture/compare 4 DMA request enable
+#define STM32F4_TIMER_DIER_CC3DE BSP_BIT16(11) // Capture/compare 3 DMA request enable
+#define STM32F4_TIMER_DIER_CC2DE BSP_BIT16(10) // Capture/compare 2 DMA request enable
+#define STM32F4_TIMER_DIER_CC1DE BSP_BIT16(9) // Capture/compare 1 DMA request enable
+#define STM32F4_TIMER_DIER_UDE BSP_BIT16(8) // Update DMA request enable
+#define STM32F4_TIMER_DIER_TIE BSP_BIT16(6) // Trigger interrupt enable
+#define STM32F4_TIMER_DIER_CC4IE BSP_BIT16(4) // Capture/compare 4 interrupt request enable
+#define STM32F4_TIMER_DIER_CC3IE BSP_BIT16(3) // Capture/compare 3 interrupt request enable
+#define STM32F4_TIMER_DIER_CC2IE BSP_BIT16(2) // Capture/compare 2 interrupt request enable
+#define STM32F4_TIMER_DIER_CC1IE BSP_BIT16(1) // Capture/compare 1 interrupt request enable
+#define STM32F4_TIMER_DIER_UIE BSP_BIT16(0) // Update interrupt request enable
+
+ uint16_t reserved_0e;
+ uint16_t sr; // Status register
+#define STM32F4_TIMER_SR_CC4OF BSP_BIT16(12) // Capture/compare 4 overcapture flag
+#define STM32F4_TIMER_SR_CC3OF BSP_BIT16(11) // Capture/compare 3 overcapture flag
+#define STM32F4_TIMER_SR_CC2OF BSP_BIT16(10) // Capture/compare 2 overcapture flag
+#define STM32F4_TIMER_SR_CC1OF BSP_BIT16(9) // Capture/compare 1 overcapture flag
+#define STM32F4_TIMER_SR_TIF BSP_BIT16(6) // Trigger interrupt flag
+#define STM32F4_TIMER_SR_CC4IF BSP_BIT16(4) // Capture/compare 4 interrupt flag
+#define STM32F4_TIMER_SR_CC3IF BSP_BIT16(3) // Capture/compare 3 interrupt flag
+#define STM32F4_TIMER_SR_CC2IF BSP_BIT16(2) // Capture/compare 2 interrupt flag
+#define STM32F4_TIMER_SR_CC1IF BSP_BIT16(1) // Capture/compare 1 interrupt flag
+#define STM32F4_TIMER_SR_UIF BSP_BIT16(0) // Update interrupt flag
+ uint16_t reserved_12;
+ uint16_t egr; // Event generation register
+#define STM32F4_TIMER_EGR_TG BSP_BIT16(6) // Trigger event
+#define STM32F4_TIMER_EGR_CC4G BSP_BIT16(4) // Capture/compare 4 event
+#define STM32F4_TIMER_EGR_CC3G BSP_BIT16(3) // Capture/compare 3 generation)
+#define STM32F4_TIMER_EGR_CC2G BSP_BIT16(2) // Capture/compare 2 generation)
+#define STM32F4_TIMER_EGR_CC1G BSP_BIT16(1) // Capture/compare 1 generation)
+#define STM32F4_TIMER_EGR_UG BSP_BIT16(0) // Update event
+ uint16_t reserved_16;
+ uint16_t ccmr1; // Capture / compare mode register 1
+#define STM32F4_TIMER_CCMR1_OC2CE BSP_BIT16(15) // Output compare 2 clear enable
+#define STM32F4_TIMER_CCMR1_OC2M(val) BSP_FLD16(val, 12, 14)
+#define STM32F4_TIMER_CCMR1_OC2M_GET(reg) BSP_FLD16GET(reg, 12, 14)
+#define STM32F4_TIMER_CCMR1_OC2M_SET(reg, val) BSP_FLD16SET(reg, val, 12, 14)
+#define STM32F4_TIMER_CCMR1_OC2M_FROZEN STM32F4_TIMER_CCMR1_OC2M(0)
+#define STM32F4_TIMER_CCMR1_OC2M_ACTIVE STM32F4_TIMER_CCMR1_OC2M(1)
+#define STM32F4_TIMER_CCMR1_OC2M_INACTIVE STM32F4_TIMER_CCMR1_OC2M(2)
+#define STM32F4_TIMER_CCMR1_OC2M_TOGGLE STM32F4_TIMER_CCMR1_OC2M(3)
+#define STM32F4_TIMER_CCMR1_OC2M_FORCE_LOW STM32F4_TIMER_CCMR1_OC2M(4)
+#define STM32F4_TIMER_CCMR1_OC2M_FORCE_HIGH STM32F4_TIMER_CCMR1_OC2M(5)
+#define STM32F4_TIMER_CCMR1_OC2M_PWM1 STM32F4_TIMER_CCMR1_OC2M(6)
+#define STM32F4_TIMER_CCMR1_OC2M_PWM2 STM32F4_TIMER_CCMR1_OC2M(7)
+#define STM32F4_TIMER_CCMR1_OC2PE BSP_BIT16(11) // Output compare 2 preload enable
+#define STM32F4_TIMER_CCMR1_OC2FE BSP_BIT16(10) // Output compare 2 fast enable
+#define STM32F4_TIMER_CCMR1_CC2S(val) BSP_FLD16(val, 8, 9)
+#define STM32F4_TIMER_CCMR1_CC2S_GET(reg) BSP_FLD16GET(reg, 8, 9)
+#define STM32F4_TIMER_CCMR1_CC2S_SET(reg, val) BSP_FLD16SET(reg, val, 8, 9)
+#define STM32F4_TIMER_CCMR1_CC2S_OUTPUT STM32F4_TIMER_CCMR1_OC2S(0)
+#define STM32F4_TIMER_CCMR1_CC2S_TI2 STM32F4_TIMER_CCMR1_OC2S(1)
+#define STM32F4_TIMER_CCMR1_CC2S_TI1 STM32F4_TIMER_CCMR1_OC2S(2)
+#define STM32F4_TIMER_CCMR1_CC2S_TRC STM32F4_TIMER_CCMR1_OC2S(3)
+#define STM32F4_TIMER_CCMR1_OC1CE BSP_BIT16(7) // Output compare 1 clear enable
+#define STM32F4_TIMER_CCMR1_OC1M(val) BSP_FLD16(val, 4, 6)
+#define STM32F4_TIMER_CCMR1_OC1M_GET(reg) BSP_FLD16GET(reg, 4, 6)
+#define STM32F4_TIMER_CCMR1_OC1M_SET(reg, val) BSP_FLD16SET(reg, val, 4, 6)
+#define STM32F4_TIMER_CCMR1_OC1M_FROZEN STM32F4_TIMER_CCMR1_OC1M(0)
+#define STM32F4_TIMER_CCMR1_OC1M_ACTIVE STM32F4_TIMER_CCMR1_OC1M(1)
+#define STM32F4_TIMER_CCMR1_OC1M_INACTIVE STM32F4_TIMER_CCMR1_OC1M(2)
+#define STM32F4_TIMER_CCMR1_OC1M_TOGGLE STM32F4_TIMER_CCMR1_OC1M(3)
+#define STM32F4_TIMER_CCMR1_OC1M_FORCE_LOW STM32F4_TIMER_CCMR1_OC1M(4)
+#define STM32F4_TIMER_CCMR1_OC1M_FORCE_HIGH STM32F4_TIMER_CCMR1_OC1M(5)
+#define STM32F4_TIMER_CCMR1_OC1M_PWM1 STM32F4_TIMER_CCMR1_OC1M(6)
+#define STM32F4_TIMER_CCMR1_OC1M_PWM2 STM32F4_TIMER_CCMR1_OC1M(7)
+#define STM32F4_TIMER_CCMR1_OC1PE BSP_BIT16(3) // Output compare 1 preload enable
+#define STM32F4_TIMER_CCMR1_OC1FE BSP_BIT16(2) // Output compare 1 fast enable
+#define STM32F4_TIMER_CCMR1_CC1S(val) BSP_FLD16(val, 0, 1)
+#define STM32F4_TIMER_CCMR1_CC1S_GET(reg) BSP_FLD16GET(reg, 0, 1)
+#define STM32F4_TIMER_CCMR1_CC1S_SET(reg, val) BSP_FLD16SET(reg, val, 0, 1)
+#define STM32F4_TIMER_CCMR1_CC1S_OUTPUT STM32F4_TIMER_CCMR1_OC1S(0)
+#define STM32F4_TIMER_CCMR1_CC1S_TI2 STM32F4_TIMER_CCMR1_OC1S(1)
+#define STM32F4_TIMER_CCMR1_CC1S_TI1 STM32F4_TIMER_CCMR1_OC1S(2)
+#define STM32F4_TIMER_CCMR1_CC1S_TRC STM32F4_TIMER_CCMR1_OC1S(3)
+ uint16_t reserved_1a;
+ uint16_t ccmr2; // Capture / compare mode register 2
+#define STM32F4_TIMER_CCMR2_OC4CE BSP_BIT16(15) // Output compare 4 clear enable
+#define STM32F4_TIMER_CCMR2_OC4M(val) BSP_FLD16(val, 12, 14)
+#define STM32F4_TIMER_CCMR2_OC4M_GET(reg) BSP_FLD16GET(reg, 12, 14)
+#define STM32F4_TIMER_CCMR2_OC4M_SET(reg, val) BSP_FLD16SET(reg, val, 12, 14)
+#define STM32F4_TIMER_CCMR2_OC4M_FROZEN STM32F4_TIMER_CCMR2_OC4M(0)
+#define STM32F4_TIMER_CCMR2_OC4M_ACTIVE STM32F4_TIMER_CCMR2_OC4M(1)
+#define STM32F4_TIMER_CCMR2_OC4M_INACTIVE STM32F4_TIMER_CCMR2_OC4M(2)
+#define STM32F4_TIMER_CCMR2_OC4M_TOGGLE STM32F4_TIMER_CCMR2_OC4M(3)
+#define STM32F4_TIMER_CCMR2_OC4M_FORCE_LOW STM32F4_TIMER_CCMR2_OC4M(4)
+#define STM32F4_TIMER_CCMR2_OC4M_FORCE_HIGH STM32F4_TIMER_CCMR2_OC4M(5)
+#define STM32F4_TIMER_CCMR2_OC4M_PWM1 STM32F4_TIMER_CCMR2_OC4M(6)
+#define STM32F4_TIMER_CCMR2_OC4M_PWM2 STM32F4_TIMER_CCMR2_OC4M(7)
+#define STM32F4_TIMER_CCMR2_OC4PE BSP_BIT16(11) // Output compare 4 preload enable
+#define STM32F4_TIMER_CCMR2_OC4FE BSP_BIT16(10) // Output compare 4 fast enable
+#define STM32F4_TIMER_CCMR2_CC4S(val) BSP_FLD16(val, 8, 9)
+#define STM32F4_TIMER_CCMR2_CC4S_GET(reg) BSP_FLD16GET(reg, 8, 9)
+#define STM32F4_TIMER_CCMR2_CC4S_SET(reg, val) BSP_FLD16SET(reg, val, 8, 9)
+#define STM32F4_TIMER_CCMR2_CC4S_OUTPUT STM32F4_TIMER_CCMR2_OC4S(0)
+#define STM32F4_TIMER_CCMR2_CC4S_TI2 STM32F4_TIMER_CCMR2_OC4S(1)
+#define STM32F4_TIMER_CCMR2_CC4S_TI1 STM32F4_TIMER_CCMR2_OC4S(2)
+#define STM32F4_TIMER_CCMR2_CC4S_TRC STM32F4_TIMER_CCMR2_OC4S(3)
+#define STM32F4_TIMER_CCMR2_OC3CE BSP_BIT16(7) // Output compare 3 clear enable
+#define STM32F4_TIMER_CCMR2_OC3M(val) BSP_FLD16(val, 4, 6)
+#define STM32F4_TIMER_CCMR2_OC3M_GET(reg) BSP_FLD16GET(reg, 4, 6)
+#define STM32F4_TIMER_CCMR2_OC3M_SET(reg, val) BSP_FLD16SET(reg, val, 4, 6)
+#define STM32F4_TIMER_CCMR2_OC3M_FROZEN STM32F4_TIMER_CCMR2_OC3M(0)
+#define STM32F4_TIMER_CCMR2_OC3M_ACTIVE STM32F4_TIMER_CCMR2_OC3M(1)
+#define STM32F4_TIMER_CCMR2_OC3M_INACTIVE STM32F4_TIMER_CCMR2_OC3M(2)
+#define STM32F4_TIMER_CCMR2_OC3M_TOGGLE STM32F4_TIMER_CCMR2_OC3M(3)
+#define STM32F4_TIMER_CCMR2_OC3M_FORCE_LOW STM32F4_TIMER_CCMR2_OC3M(4)
+#define STM32F4_TIMER_CCMR2_OC3M_FORCE_HIGH STM32F4_TIMER_CCMR2_OC3M(5)
+#define STM32F4_TIMER_CCMR2_OC3M_PWM1 STM32F4_TIMER_CCMR2_OC3M(6)
+#define STM32F4_TIMER_CCMR2_OC3M_PWM2 STM32F4_TIMER_CCMR2_OC3M(7)
+#define STM32F4_TIMER_CCMR2_OC3PE BSP_BIT16(3) // Output compare 3 preload enable
+#define STM32F4_TIMER_CCMR2_OC3FE BSP_BIT16(2) // Output compare 3 fast enable
+#define STM32F4_TIMER_CCMR2_CC3S(val) BSP_FLD16(val, 0, 1)
+#define STM32F4_TIMER_CCMR2_CC3S_GET(reg) BSP_FLD16GET(reg, 0, 1)
+#define STM32F4_TIMER_CCMR2_CC3S_SET(reg, val) BSP_FLD16SET(reg, val, 0, 1)
+#define STM32F4_TIMER_CCMR2_CC3S_OUTPUT STM32F4_TIMER_CCMR2_OC3S(0)
+#define STM32F4_TIMER_CCMR2_CC3S_TI2 STM32F4_TIMER_CCMR2_OC3S(1)
+#define STM32F4_TIMER_CCMR2_CC3S_TI1 STM32F4_TIMER_CCMR2_OC3S(2)
+#define STM32F4_TIMER_CCMR2_CC3S_TRC STM32F4_TIMER_CCMR2_OC3S(3)
+ uint16_t reserved_1e;
+ uint16_t ccer; // Capture / compare enable register
+#define STM32F4_TIMER_CCER_CC4NP BSP_BIT16(15) // Capture / compare 4 output polarity
+#define STM32F4_TIMER_CCER_CC4P BSP_BIT16(13) // Capture / compare 4 output polarity
+#define STM32F4_TIMER_CCER_CC4E BSP_BIT16(12) // Capture / compare 4 output enable
+#define STM32F4_TIMER_CCER_CC3NP BSP_BIT16(11) // Capture / compare 3 output polarity
+#define STM32F4_TIMER_CCER_CC3P BSP_BIT16(9) // Capture / compare 3 output polarity
+#define STM32F4_TIMER_CCER_CC3E BSP_BIT16(8) // Capture / compare 3 output enable
+#define STM32F4_TIMER_CCER_CC2NP BSP_BIT16(7) // Capture / compare 2 output polarity
+#define STM32F4_TIMER_CCER_CC2P BSP_BIT16(5) // Capture / compare 2 output polarity
+#define STM32F4_TIMER_CCER_CC2E BSP_BIT16(4) // Capture / compare 2 output enable
+#define STM32F4_TIMER_CCER_CC1NP BSP_BIT16(3) // Capture / compare 1 output polarity
+#define STM32F4_TIMER_CCER_CC1P BSP_BIT16(1) // Capture / compare 1 output polarity
+#define STM32F4_TIMER_CCER_CC1E BSP_BIT16(0) // Capture / compare 1 output enable
+ uint16_t reserved_22;
+ uint32_t cnt; // Counter register
+#define STM32F4_TIMER_DR(val) BSP_FLD32(val, 0, 31)
+#define STM32F4_TIMER_DR_GET(reg) BSP_FLD32GET(reg, 0, 31)
+#define STM32F4_TIMER_DR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 31)
+ uint16_t psc; // Prescalar
+ uint16_t reserved_2a;
+ uint32_t arr; // Auto-reload register
+ uint16_t rcr; // Repetition counter register
+ uint16_t rserved_32;
+ uint32_t ccr[4];// Capture / compare registers
+ uint16_t bdtr; // Break and dead-time register
+ uint16_t reserved_46;
+ uint16_t dcr; // DMA control register
+ uint16_t reserved_4a;
+ uint16_t dmar; // DMA address for full transfer
+ uint16_t reserved_4e;
+ uint16_t or; // Option register
+ uint16_t reserved_52;
+} __attribute__ ((packed));
+typedef struct stm32f4_tim_s stm32f4_tim;
+
+#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_TIM_H */
diff --git a/c/src/lib/libbsp/arm/stm32f4/preinstall.am b/c/src/lib/libbsp/arm/stm32f4/preinstall.am
index a75e3d0..61f4549 100644
--- a/c/src/lib/libbsp/arm/stm32f4/preinstall.am
+++ b/c/src/lib/libbsp/arm/stm32f4/preinstall.am
@@ -117,6 +117,10 @@ $(PROJECT_INCLUDE)/bsp/stm32f10xxx_exti.h: include/stm32f10xxx_exti.h $(PROJECT_
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f10xxx_exti.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f10xxx_exti.h
+$(PROJECT_INCLUDE)/bsp/stm32f4xxxx_exti.h: include/stm32f4xxxx_exti.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_exti.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_exti.h
+
$(PROJECT_INCLUDE)/bsp/stm32f4xxxx_gpio.h: include/stm32f4xxxx_gpio.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_gpio.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_gpio.h
@@ -125,6 +129,22 @@ $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_rcc.h: include/stm32f4xxxx_rcc.h $(PROJECT_IN
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_rcc.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_rcc.h
+$(PROJECT_INCLUDE)/bsp/stm32f4xxxx_pwr.h: include/stm32f4xxxx_pwr.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_pwr.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_pwr.h
+
+$(PROJECT_INCLUDE)/bsp/stm32f4xxxx_syscfg.h: include/stm32f4xxxx_syscfg.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_syscfg.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_syscfg.h
+
+$(PROJECT_INCLUDE)/bsp/stm32f4xxxx_tim.h: include/stm32f4xxxx_tim.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_tim.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_tim.h
+
+$(PROJECT_INCLUDE)/bsp/stm32f4xxxx_flash.h: include/stm32f4xxxx_flash.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_flash.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_flash.h
+
$(PROJECT_INCLUDE)/bsp/stm32_i2c.h: include/stm32_i2c.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32_i2c.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32_i2c.h
diff --git a/c/src/lib/libbsp/arm/stm32f4/startup/bspstart.c b/c/src/lib/libbsp/arm/stm32f4/startup/bspstart.c
old mode 100644
new mode 100755
index 3bea8f9..5f0d0ba
--- a/c/src/lib/libbsp/arm/stm32f4/startup/bspstart.c
+++ b/c/src/lib/libbsp/arm/stm32f4/startup/bspstart.c
@@ -20,6 +20,8 @@
void bsp_start(void)
{
+ stm32f4_rcc_init();
+
stm32f4_gpio_set_config_array(&stm32f4_start_config_gpio [0]);
bsp_interrupt_initialize();
diff --git a/c/src/lib/libbsp/arm/stm32f4/startup/rcc.c b/c/src/lib/libbsp/arm/stm32f4/startup/rcc.c
old mode 100644
new mode 100755
index a5f3f79..1610ca8
--- a/c/src/lib/libbsp/arm/stm32f4/startup/rcc.c
+++ b/c/src/lib/libbsp/arm/stm32f4/startup/rcc.c
@@ -17,6 +17,151 @@
#include <rtems.h>
+/*
+ *=============================================================================
+ * Supported STM32F4xx device revision | Rev A
+ *-----------------------------------------------------------------------------
+ * System Clock source | PLL (HSE)
+ *-----------------------------------------------------------------------------
+ * SYSCLK(Hz) | 168000000
+ *-----------------------------------------------------------------------------
+ * HCLK(Hz) | 168000000
+ *-----------------------------------------------------------------------------
+ * AHB Prescaler | 1
+ *-----------------------------------------------------------------------------
+ * APB1 Prescaler | 4
+ *-----------------------------------------------------------------------------
+ * APB2 Prescaler | 2
+ *-----------------------------------------------------------------------------
+ * HSE Frequency(Hz) | 8000000
+ *-----------------------------------------------------------------------------
+ * PLL_M | 8
+ *-----------------------------------------------------------------------------
+ * PLL_N | 336
+ *-----------------------------------------------------------------------------
+ * PLL_P | 2
+ *-----------------------------------------------------------------------------
+ * PLL_Q | 7
+ *-----------------------------------------------------------------------------
+ * PLLI2S_N | NA
+ *-----------------------------------------------------------------------------
+ * PLLI2S_R | NA
+ *-----------------------------------------------------------------------------
+ * I2S input clock | NA
+ *-----------------------------------------------------------------------------
+ * VDD(V) | 3.3
+ *-----------------------------------------------------------------------------
+ * Main regulator output voltage | Scale1 mode
+ *-----------------------------------------------------------------------------
+ * Flash Latency(WS) | 5
+ *-----------------------------------------------------------------------------
+ * Prefetch Buffer | OFF
+ *-----------------------------------------------------------------------------
+ * Instruction cache | ON
+ *-----------------------------------------------------------------------------
+ * Data cache | ON
+ *-----------------------------------------------------------------------------
+ * Require 48MHz for USB OTG FS, | Enabled
+ * SDIO and RNG clock |
+ *-----------------------------------------------------------------------------
+ */
+void
+stm32f4_rcc_init (void)
+{
+ uint32_t cnt = 0;
+ uint32_t hserdy = 0;
+
+ // Init clocks
+ volatile stm32f4_rcc *rcc = STM32F4_RCC;
+ volatile stm32f4_pwr *pwr = STM32F4_PWR;
+ volatile stm32f4_flash *flash = STM32F4_FLASH;
+
+ // Set HSI on
+ rcc->cr |= STM32F4_RCC_CR_HSION;
+
+ // Reset CFGR
+ rcc->cfgr = 0;
+
+ // Reset HSEON, CSSON and PLLON bits
+ rcc->cr &= (uint32_t) ~(STM32F4_RCC_CR_PLLON | STM32F4_RCC_CR_CSSON | STM32F4_RCC_CR_HSEON);
+
+ // Reset PLLCFGR register
+ rcc->pllcfgr = 0x24003010;
+
+ // Reset HSEBYP bit
+ rcc->cr &= (uint32_t) ~(STM32F4_RCC_CR_HSEBYP);
+
+ // Enable HSE
+ rcc->cr |= STM32F4_RCC_CR_HSEON;
+
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ hserdy = rcc->cr & STM32F4_RCC_CR_HSERDY;
+ cnt++;
+ } while (!hserdy && (cnt < 2000));
+
+ if (!hserdy)
+ {
+ // HSE clock did not start ..
+
+ // Reset HSEON bit
+ rcc->cr &= (uint32_t) ~(STM32F4_RCC_CR_HSEON);
+ while(1)
+ ;
+ }
+
+ /* Select regulator voltage output Scale 1 mode, System frequency up to 168 MHz */
+ //rcc->apbenr[0] |= STM32F4_RCC_PWR;
+ stm32f4_rcc_set_clock(STM32F4_RCC_PWR, true);
+ pwr->cr |= STM32F4_PWR_CR_VOS;
+
+ // HCLK = SYSCLK / 1
+ rcc->cfgr |= STM32F4_RCC_CFGR_HPRE_DIV2;
+
+ // PCLK2 = HCLK / 2
+ rcc->cfgr |= STM32F4_RCC_CFGR_PPRE2_DIV2;
+
+ // PCLK1 = HCLK / 4
+ rcc->cfgr |= STM32F4_RCC_CFGR_PPRE1_DIV4;
+
+ rcc->cfgr |= STM32F4_RCC_CFGR_MCO2_DIV2;
+ rcc->cfgr |= STM32F4_RCC_CFGR_MCO2_PLL;
+
+ /* Configure the main PLL */
+ rcc->pllcfgr = STM32F4_RCC_PLLCFGR_PLLM(8)
+ | STM32F4_RCC_PLLCFGR_PLLN(336)
+ | STM32F4_RCC_PLLCFGR_PLLP_2
+ | STM32F4_RCC_PLLCFGR_PLLQ(7)
+ | STM32F4_RCC_PLLCFGR_SRC_HSE;
+
+ // Enable the main PLL
+ rcc->cr |= STM32F4_RCC_CR_PLLON;
+
+ /* Wait till the main PLL is ready */
+ while ((rcc->cr & STM32F4_RCC_CR_PLLRDY) == 0)
+ {
+ }
+
+ // Configure Flash prefetch, Instruction cache, Data cache and wait state
+ flash->acr = STM32F4_FLASH_ACR_ICEN | STM32F4_FLASH_ACR_DCEN
+ | STM32F4_FLASH_ACR_PRFTEN | STM32F4_FLASH_ACR_LATENCY(5);
+
+ if (STM32F4_FLASH_ACR_LATENCY_GET(flash->acr) != 5)
+ {
+ while (1)
+ ;
+ }
+
+ // Select the main PLL as system clock source
+ rcc->cfgr = STM32F4_RCC_CFGR_SW_SET(rcc->cfgr, STM32F4_RCC_CFGR_SW_PLL);
+
+ // Wait till the main PLL is used as system clock source
+ while (STM32F4_RCC_CFGR_SWS_GET(rcc->cfgr) != STM32F4_RCC_CFGR_SWS_GET(STM32F4_RCC_CFGR_SWS_PLL))
+ {
+ }
+}
+
static void rcc_set(
stm32f4_rcc_index index,
bool set,
--
1.8.4.2
>From 56ad79fe132f776dc86dd53ba3a9764ebb57dd11 Mon Sep 17 00:00:00 2001
From: Chris Nott <chrisn at vl.com.au>
Date: Wed, 29 Jan 2014 10:58:35 -0800
Subject: [PATCH 4/8] Increased CPU clk to 168MHz
---
c/src/lib/libbsp/arm/stm32f4/startup/rcc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/c/src/lib/libbsp/arm/stm32f4/startup/rcc.c b/c/src/lib/libbsp/arm/stm32f4/startup/rcc.c
index 1610ca8..47ada3f 100755
--- a/c/src/lib/libbsp/arm/stm32f4/startup/rcc.c
+++ b/c/src/lib/libbsp/arm/stm32f4/startup/rcc.c
@@ -117,7 +117,7 @@ stm32f4_rcc_init (void)
pwr->cr |= STM32F4_PWR_CR_VOS;
// HCLK = SYSCLK / 1
- rcc->cfgr |= STM32F4_RCC_CFGR_HPRE_DIV2;
+ rcc->cfgr |= STM32F4_RCC_CFGR_HPRE_DIV1;
// PCLK2 = HCLK / 2
rcc->cfgr |= STM32F4_RCC_CFGR_PPRE2_DIV2;
@@ -125,8 +125,8 @@ stm32f4_rcc_init (void)
// PCLK1 = HCLK / 4
rcc->cfgr |= STM32F4_RCC_CFGR_PPRE1_DIV4;
- rcc->cfgr |= STM32F4_RCC_CFGR_MCO2_DIV2;
- rcc->cfgr |= STM32F4_RCC_CFGR_MCO2_PLL;
+// rcc->cfgr |= STM32F4_RCC_CFGR_MCO2_DIV2;
+// rcc->cfgr |= STM32F4_RCC_CFGR_MCO2_SYSCLK;
/* Configure the main PLL */
rcc->pllcfgr = STM32F4_RCC_PLLCFGR_PLLM(8)
--
1.8.4.2
>From 67135268db600d5eb0bee0317aa165b07c4005c1 Mon Sep 17 00:00:00 2001
From: Chris Nott <chrisn at vl.com.au>
Date: Mon, 3 Mar 2014 02:47:55 -0800
Subject: [PATCH 5/8] Added OTG FS register definitions
---
.../libbsp/arm/stm32f4/include/stm32f4xxxx_otgfs.h | 445 +++++++++++++++++++++
1 file changed, 445 insertions(+)
create mode 100755 c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_otgfs.h
diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_otgfs.h b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_otgfs.h
new file mode 100755
index 0000000..edac985
--- /dev/null
+++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_otgfs.h
@@ -0,0 +1,445 @@
+/*
+ * Copyright (c) 2013 Chris Nott. All rights reserved.
+ *
+ * Virtual Logic
+ * 21-25 King St.
+ * Rockdale NSW 2216
+ * Australia
+ * <rtems at vl.com.au>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_OTGFS_H
+#define LIBBSP_ARM_STM32F4_STM32F4XXXX_OTGFS_H
+
+#include <bsp/utility.h>
+
+#define USB_OTG_NUM_EPS 4
+#define USB_OTG_MAX_TX_FIFOS 4
+
+#define USB_FIFO_BASE 0x1000
+#define USB_FIFO_OFFS 0x1000
+
+struct stm32f4_otgfs_s {
+ uint32_t gotgctl; // 0x00: Control and status register
+#define STM32F4_OTGFS_GOTGCTL_BSVLD BSP_BIT32(19) // B-session valid
+#define STM32F4_OTGFS_GOTGCTL_ASVLD BSP_BIT32(18) // A-session valid
+#define STM32F4_OTGFS_GOTGCTL_DBCT BSP_BIT32(17) // Debounce time
+#define STM32F4_OTGFS_GOTGCTL_CIDSTS BSP_BIT32(16) // Connector ID status
+#define STM32F4_OTGFS_GOTGCTL_DHNPEN BSP_BIT32(11) // Device HNP enable
+#define STM32F4_OTGFS_GOTGCTL_HSHNPEN BSP_BIT32(10) // Host set HNP enable
+#define STM32F4_OTGFS_GOTGCTL_HNPRQ BSP_BIT32(9) // HNP request
+#define STM32F4_OTGFS_GOTGCTL_HNGSCS BSP_BIT32(8) // Host negotiation status
+#define STM32F4_OTGFS_GOTGCTL_SRQ BSP_BIT32(1) // Session request
+#define STM32F4_OTGFS_GOTGCTL_SRQSCS BSP_BIT32(0) // Session request success
+
+ uint32_t gotgint; // 0x04: Interrupt register
+#define STM32F4_OTGFS_GOTGINT_DBCDNE BSP_BIT32(19) // Debounce done
+#define STM32F4_OTGFS_GOTGINT_ADTOCHG BSP_BIT32(18) // A-device timeout change
+#define STM32F4_OTGFS_GOTGINT_HNGDET BSP_BIT32(17) // Host negotiation detected
+#define STM32F4_OTGFS_GOTGINT_HNSSCHG BSP_BIT32(9) // Host negotiation success status change
+#define STM32F4_OTGFS_GOTGINT_SRSSCHG BSP_BIT32(8) // Session request status change
+#define STM32F4_OTGFS_GOTGINT_SEDET BSP_BIT32(2) // Session end detected
+
+ uint32_t gahbcfg; // 0x08: AHB configuration register
+#define STM32F4_OTGFS_GAHBCFG_PTXFELVL BSP_BIT32(8) // Periodic txfifo empty level
+#define STM32F4_OTGFS_GAHBCFG_TXFELVL BSP_BIT32(7) // Txfifo empty level
+#define STM32F4_OTGFS_GAHBCFG_GINTMSK BSP_BIT32(0) // Global interrupt mask
+
+ uint32_t gusbcfg; // 0x0C: USB configuration register
+#define STM32F4_OTGFS_GUSBCFG_CTXPKT BSP_BIT32(31) // Corrupt TX packet
+#define STM32F4_OTGFS_GUSBCFG_FDMOD BSP_BIT32(30) // Force device mode
+#define STM32F4_OTGFS_GUSBCFG_FHMOD BSP_BIT32(29) // Force host mode
+#define STM32F4_OTGFS_GUSBCFG_TRDT(val) BSP_FLD32(val, 10, 13) // USB turnaround time
+#define STM32F4_OTGFS_GUSBCFG_TRDT_GET(reg) BSP_FLD32GET(reg, 10, 13)
+#define STM32F4_OTGFS_GUSBCFG_TRDT_SET(reg, val) BSP_FLD32SET(reg, val, 10, 13)
+#define STM32F4_OTGFS_GUSBCFG_HNPCAP BSP_BIT32(9) // HNP-capable
+#define STM32F4_OTGFS_GUSBCFG_SRPCAP BSP_BIT32(8) // SRP-capable
+#define STM32F4_OTGFS_GUSBCFG_PHYSEL BSP_BIT32(6) // Full speed serial transceiver select
+#define STM32F4_OTGFS_GUSBCFG_TOCAL(val) BSP_FLD32(val, 0, 2) // FS timeout calibration
+#define STM32F4_OTGFS_GUSBCFG_TOCAL_GET(reg) BSP_FLD32GET(reg, 0, 2)
+#define STM32F4_OTGFS_GUSBCFG_TOCAL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2)
+
+ uint32_t grstctl; // 0x10: Reset register
+#define STM32F4_OTGFS_GRSTCTL_AHBIDL BSP_BIT32(31) // AHB master idle
+#define STM32F4_OTGFS_GRSTCTL_TXFNUM(val) BSP_FLD32(val, 6, 10) // Tx fifo number
+#define STM32F4_OTGFS_GRSTCTL_TXFNUM_GET(reg) BSP_FLD32GET(reg, 6, 10)
+#define STM32F4_OTGFS_GRSTCTL_TXFNUM_SET(reg, val) BSP_FLD32SET(reg, val, 6, 10)
+#define STM32F4_OTGFS_GRSTCTL_TXFNUM_ALL STM32F4_OTGFS_GRSTCTL_TXFNUM(0x10)
+#define STM32F4_OTGFS_GRSTCTL_TXFFLSH BSP_BIT32(5) // TX fifo flush
+#define STM32F4_OTGFS_GRSTCTL_RXFFLSH BSP_BIT32(4) // RX fifo flush
+#define STM32F4_OTGFS_GRSTCTL_FCRST BSP_BIT32(2) // Host frame counter reset
+#define STM32F4_OTGFS_GRSTCTL_HSRST BSP_BIT32(1) // HCLK soft reset
+#define STM32F4_OTGFS_GRSTCTL_CSRST BSP_BIT32(0) // Core soft reset
+
+ uint32_t gintsts; // 0x14: Core interrupt register
+#define STM32F4_OTGFS_GINTSTS_WKUPINT BSP_BIT32(31) // Resume / remote wakeup detected interrupt
+#define STM32F4_OTGFS_GINTSTS_SRQINT BSP_BIT32(30) // Session request / new session detected interrupt
+#define STM32F4_OTGFS_GINTSTS_DISCINT BSP_BIT32(29) // Disconnect detected interrupt
+#define STM32F4_OTGFS_GINTSTS_CIDSCHG BSP_BIT32(28) // Connector ID status change
+#define STM32F4_OTGFS_GINTSTS_PTXFE BSP_BIT32(26) // Periodic TX fifo empty
+#define STM32F4_OTGFS_GINTSTS_HCINT BSP_BIT32(25) // Host channels interrupt
+#define STM32F4_OTGFS_GINTSTS_HPRTINT BSP_BIT32(24) // Host port interrupt
+#define STM32F4_OTGFS_GINTSTS_IPXFR BSP_BIT32(21) // Incomplete periodic transfer
+#define STM32F4_OTGFS_GINTSTS_IISOOXFR BSP_BIT32(21) // Incomplete isochronous OUT transfer
+#define STM32F4_OTGFS_GINTSTS_IISOIXFR BSP_BIT32(20) // Incomplete isochronous IN transfer
+#define STM32F4_OTGFS_GINTSTS_OEPINT BSP_BIT32(19) // OUT endpoint interrupt
+#define STM32F4_OTGFS_GINTSTS_IEPINT BSP_BIT32(18) // IN endpoint interrupt
+#define STM32F4_OTGFS_GINTSTS_EOPF BSP_BIT32(15) // End of periodic frame interrupt
+#define STM32F4_OTGFS_GINTSTS_ISOODRP BSP_BIT32(14) // Isochronous OUT packet dropped interrupt
+#define STM32F4_OTGFS_GINTSTS_ENUMDNE BSP_BIT32(13) // Enumeration done
+#define STM32F4_OTGFS_GINTSTS_USBRST BSP_BIT32(12) // USB reset
+#define STM32F4_OTGFS_GINTSTS_USBSUSP BSP_BIT32(11) // USB suspend
+#define STM32F4_OTGFS_GINTSTS_ESUSP BSP_BIT32(10) // Early suspend
+#define STM32F4_OTGFS_GINTSTS_GONAKEFF BSP_BIT32(7) // Global OUT NAK effective
+#define STM32F4_OTGFS_GINTSTS_GINAKEFF BSP_BIT32(6) // Global IN non-periodic NAK effective
+#define STM32F4_OTGFS_GINTSTS_NPTXFE BSP_BIT32(5) // Non-periodic TX fifo empty
+#define STM32F4_OTGFS_GINTSTS_RXFLVL BSP_BIT32(4) // RX fifo non-empty
+#define STM32F4_OTGFS_GINTSTS_SOF BSP_BIT32(3) // Start of frame
+#define STM32F4_OTGFS_GINTSTS_OTGINT BSP_BIT32(2) // OTG interrupt
+#define STM32F4_OTGFS_GINTSTS_MMIS BSP_BIT32(1) // Mode mismatch interrupt
+#define STM32F4_OTGFS_GINTSTS_CMOD BSP_BIT32(0) // Current mode of operation
+
+ uint32_t gintmsk; // 0x18: Interrupt mask register
+
+ uint32_t grxstsr; // 0x1C: Receive status debug read
+
+ uint32_t grxstsp; // 0x20: OTG status read and pop
+#define STM32F4_OTGFS_GRXSTSP_FRMNUM(val) BSP_FLD32(val, 21, 24) // Frame number
+#define STM32F4_OTGFS_GRXSTSP_FRMNUM_GET(reg) BSP_FLD32GET(reg, 21, 24)
+#define STM32F4_OTGFS_GRXSTSP_FRMNUM_SET(reg, val) BSP_FLD32SET(reg, val, 21, 24)
+#define STM32F4_OTGFS_GRXSTSP_PKTSTS(val) BSP_FLD32(val, 17, 20) // Packet status
+#define STM32F4_OTGFS_GRXSTSP_PKTSTS_GET(reg) BSP_FLD32GET(reg, 17, 20)
+#define STM32F4_OTGFS_GRXSTSP_PKTSTS_SET(reg, val) BSP_FLD32SET(reg, val, 17, 20)
+#define PKTSTS_IN_DATA (0x2)
+#define PKTSTS_IN_COMPLETE (0x3)
+#define PKTSTS_TOGGLE_ERR (0x5)
+#define PKTSTS_HALTED (0x7)
+#define PKTSTS_OUTNAK (0x1)
+#define PKTSTS_OUT_DATA (0x2)
+#define PKTSTS_OUT_COMPLETE (0x3)
+#define PKTSTS_SETUP_COMPLETE (0x4)
+#define PKTSTS_SETUP_DATA (0x6)
+#define STM32F4_OTGFS_GRXSTSP_DPIG(val) BSP_FLD32(val, 15, 16) // Data PID
+#define STM32F4_OTGFS_GRXSTSP_DPID_GET(reg) BSP_FLD32GET(reg, 15, 16)
+#define STM32F4_OTGFS_GRXSTSP_DPID_SET(reg, val) BSP_FLD32SET(reg, val, 15, 16)
+#define STM32F4_OTGFS_GRXSTSP_DPID_DATA0 STM32F4_OTGFS_GRXSTSP_PKTSTS(0x0)
+#define STM32F4_OTGFS_GRXSTSP_DPID_DATA1 STM32F4_OTGFS_GRXSTSP_PKTSTS(0x1)
+#define STM32F4_OTGFS_GRXSTSP_DPID_DATA2 STM32F4_OTGFS_GRXSTSP_PKTSTS(0x2)
+#define STM32F4_OTGFS_GRXSTSP_DPID_MDATA0 STM32F4_OTGFS_GRXSTSP_PKTSTS(0x3)
+#define STM32F4_OTGFS_GRXSTSP_BCNT(val) BSP_FLD32(val, 4, 14) // Byte count
+#define STM32F4_OTGFS_GRXSTSP_BCNT_GET(reg) BSP_FLD32GET(reg, 4, 14)
+#define STM32F4_OTGFS_GRXSTSP_BCNT_SET(reg, val) BSP_FLD32SET(reg, val, 4, 14)
+#define STM32F4_OTGFS_GRXSTSP_CHNUM(val) BSP_FLD32(val, 0, 3) // Channel number
+#define STM32F4_OTGFS_GRXSTSP_CHNUM_GET(reg) BSP_FLD32GET(reg, 0, 3)
+#define STM32F4_OTGFS_GRXSTSP_CHNUM_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
+#define STM32F4_OTGFS_GRXSTSP_EPNUM(val) BSP_FLD32(val, 0, 3) // Endpoint number
+#define STM32F4_OTGFS_GRXSTSP_EPNUM_GET(reg) BSP_FLD32GET(reg, 0, 3)
+#define STM32F4_OTGFS_GRXSTSP_EPNUM_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3)
+
+ uint32_t grxfsiz; // 0x24: Receive FIFO size register
+#define STM32F4_OTGFS_GRXFSIZ_RXFD(val) BSP_FLD32(val, 0, 15)
+#define STM32F4_OTGFS_GRXFSIZ_RXFD_GET(reg) BSP_FLD32GET(reg, 0, 15)
+#define STM32F4_OTGFS_GRXFSIZ_RXFD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15)
+#define STM32F4_OTGFS_GRXFSIZ_RXFD_MIN 16
+#define STM32F4_OTGFS_GRXFSIZ_RXFD_MAX 256
+
+ uint32_t dieptxf0; // 0x28: EP 0 transmit fifo size
+#define STM32F4_OTGFS_DIEPTXF_DEPTH(val) BSP_FLD32(val, 16, 31)
+#define STM32F4_OTGFS_DIEPTXF_DEPTH_GET(reg) BSP_FLD32GET(reg, 16, 31)
+#define STM32F4_OTGFS_DIEPTXF_DEPTH_SET(reg, val) BSP_FLD32SET(reg, val, 16, 31)
+#define STM32F4_OTGFS_DIEPTXF_DEPTH_MIN 16
+#define STM32F4_OTGFS_DIEPTXF_DEPTH_MAX 256
+#define STM32F4_OTGFS_DIEPTXF_SADDR(val) BSP_FLD32(val, 0, 15)
+#define STM32F4_OTGFS_DIEPTXF_SADDR_GET(reg) BSP_FLD32GET(reg, 0, 15)
+#define STM32F4_OTGFS_DIEPTXF_SADDR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15)
+
+ uint32_t resv2C;
+
+ uint32_t gi2cctl; // 0x30
+ uint32_t resv34; // 0x34
+
+ uint32_t gccfg; // 0x38: General core configuration register
+#define STM32F4_OTGFS_GCCFG_NOVBUSSENS BSP_BIT32(21) // Vbus sensing disable
+#define STM32F4_OTGFS_GCCFG_SOFOUTEN BSP_BIT32(20) // SOF output enable
+#define STM32F4_OTGFS_GCCFG_VBUSBSEN BSP_BIT32(19) // Vbus sensing "B" device
+#define STM32F4_OTGFS_GCCFG_VBUSASEN BSP_BIT32(18) // Vbus sensing "A" device
+#define STM32F4_OTGFS_GCCFG_PWRDWN BSP_BIT32(16) // Power down
+
+ uint32_t cid; // 0x3C: Product ID
+
+ uint32_t resv40[48]; // 0x40 - 0x9C
+
+ uint32_t hptxfsiz; // 0x100
+
+ uint32_t dieptxf[USB_OTG_MAX_TX_FIFOS]; // 0x104
+
+} __attribute__ ((packed));
+typedef struct stm32f4_otgfs_s stm32f4_otgfs;
+
+struct stm32f4_otgfs_dregs_s {
+ uint32_t dcfg; // 0x800
+#define STM32F4_OTGFS_DCFG_PFIVL(val) BSP_FLD32(val, 11, 12) // Periodic frame interval
+#define STM32F4_OTGFS_DCFG_PFIVL_GET(reg) BSP_FLD32GET(reg, 11, 12)
+#define STM32F4_OTGFS_DCFG_PFIVL_SET(reg, val) BSP_FLD32SET(reg, val, 11, 12)
+#define PFIVL_80 0
+#define PFIVL_85 1
+#define PFIVL_90 2
+#define PFIVL_95 3
+#define STM32F4_OTGFS_DCFG_DAD(val) BSP_FLD32(val, 4, 10) // Device address
+#define STM32F4_OTGFS_DCFG_DAD_GET(reg) BSP_FLD32GET(reg, 4, 10)
+#define STM32F4_OTGFS_DCFG_DAD_SET(reg, val) BSP_FLD32SET(reg, val, 4, 10)
+#define STM32F4_OTGFS_DCFG_NZLSOHSK BSP_BIT32(2) // Non-zero-length status OUT handshake
+#define STM32F4_OTGFS_DCFG_DSPD(val) BSP_FLD32(val, 0, 1) // Device speed
+#define STM32F4_OTGFS_DCFG_DSPD_GET(reg) BSP_FLD32GET(reg, 0, 1)
+#define STM32F4_OTGFS_DCFG_DSPD_SET(reg, val) BSP_FLD32SET(reg, val, 0, 1)
+#define STM32F4_OTGFS_DCFG_DSPD_FULL STM32F4_OTGFS_DCFG_DSPD(0x3)
+
+ uint32_t dctl; // 0x804
+#define STM32F4_OTGFS_DCTL_POPRGDNE BSP_BIT32(11) // Power-on programming done
+#define STM32F4_OTGFS_DCTL_CGONAK BSP_BIT32(10) // Clear global OUT NAK
+#define STM32F4_OTGFS_DCTL_SGONAK BSP_BIT32(9) // Set global OUT NAK
+#define STM32F4_OTGFS_DCTL_CGINAK BSP_BIT32(8) // Clear global IN NAK
+#define STM32F4_OTGFS_DCTL_SGINAK BSP_BIT32(7) // Set global IN NAK
+#define STM32F4_OTGFS_DCTL_TCTL(val) BSP_FLD32(val, 4, 6) // Test control
+#define STM32F4_OTGFS_DCTL_TCTL_GET(reg) BSP_FLD32GET(reg, 4, 6)
+#define STM32F4_OTGFS_DCTL_TCTL_SET(reg, val) BSP_FLD32SET(reg, val, 4, 6)
+#define STM32F4_OTGFS_DCTL_GONSTS BSP_BIT32(3) // Global OUT NAK status
+#define STM32F4_OTGFS_DCTL_GINSTS BSP_BIT32(2) // Global IN NAK status
+#define STM32F4_OTGFS_DCTL_SDIS BSP_BIT32(1) // Soft disconnect
+#define STM32F4_OTGFS_DCTL_RWUSIG BSP_BIT32(0) // Remote wakeup signalling
+
+ uint32_t dsts; // 0x808
+#define STM32F4_OTGFS_DSTS_FNSOF(val) BSP_FLD32(val, 8, 21) // Frame number of received SOF
+#define STM32F4_OTGFS_DSTS_FNSOF_GET(reg) BSP_FLD32GET(reg, 8, 21)
+#define STM32F4_OTGFS_DSTS_EERR BSP_BIT32(3) // Erratic error
+#define STM32F4_OTGFS_DSTS_ENUMSPD(val) BSP_FLD32(val, 1, 2) // Enumerated speed
+#define STM32F4_OTGFS_DSTS_ENUMSPD_GET(reg) BSP_FLD32GET(reg, 1, 2)
+#define STM32F4_OTGFS_DSTS_ENUMSPD_FULL STM32F4_OTGFS_DSTS_ENUMSPD(0x3)
+#define STM32F4_OTGFS_DSTS_SUSPSTS BSP_BIT32(0) // Suspend status
+
+ uint32_t unused4; // 0x80C
+
+ uint32_t diepmsk; // 0x810
+
+ uint32_t doepmsk; // 0x814
+
+ uint32_t daint; // 0x818
+#define STM32F4_OTGFS_DAINT_OEPINT15 BSP_BIT32(31) // OUT endpoint 15 interrupt
+#define STM32F4_OTGFS_DAINT_OEPINT14 BSP_BIT32(30) // OUT endpoint 14 interrupt
+#define STM32F4_OTGFS_DAINT_OEPINT13 BSP_BIT32(29) // OUT endpoint 13 interrupt
+#define STM32F4_OTGFS_DAINT_OEPINT12 BSP_BIT32(28) // OUT endpoint 12 interrupt
+#define STM32F4_OTGFS_DAINT_OEPINT11 BSP_BIT32(27) // OUT endpoint 11 interrupt
+#define STM32F4_OTGFS_DAINT_OEPINT10 BSP_BIT32(26) // OUT endpoint 10 interrupt
+#define STM32F4_OTGFS_DAINT_OEPINT9 BSP_BIT32(25) // OUT endpoint 9 interrupt
+#define STM32F4_OTGFS_DAINT_OEPINT8 BSP_BIT32(24) // OUT endpoint 8 interrupt
+#define STM32F4_OTGFS_DAINT_OEPINT7 BSP_BIT32(23) // OUT endpoint 7 interrupt
+#define STM32F4_OTGFS_DAINT_OEPINT6 BSP_BIT32(22) // OUT endpoint 6 interrupt
+#define STM32F4_OTGFS_DAINT_OEPINT5 BSP_BIT32(21) // OUT endpoint 5 interrupt
+#define STM32F4_OTGFS_DAINT_OEPINT4 BSP_BIT32(20) // OUT endpoint 4 interrupt
+#define STM32F4_OTGFS_DAINT_OEPINT3 BSP_BIT32(19) // OUT endpoint 3 interrupt
+#define STM32F4_OTGFS_DAINT_OEPINT2 BSP_BIT32(18) // OUT endpoint 2 interrupt
+#define STM32F4_OTGFS_DAINT_OEPINT1 BSP_BIT32(17) // OUT endpoint 1 interrupt
+#define STM32F4_OTGFS_DAINT_OEPINT0 BSP_BIT32(16) // OUT endpoint 0 interrupt
+#define STM32F4_OTGFS_DAINT_IEPINT15 BSP_BIT32(15) // IN endpoint 15 interrupt
+#define STM32F4_OTGFS_DAINT_IEPINT14 BSP_BIT32(14) // IN endpoint 14 interrupt
+#define STM32F4_OTGFS_DAINT_IEPINT13 BSP_BIT32(13) // IN endpoint 13 interrupt
+#define STM32F4_OTGFS_DAINT_IEPINT12 BSP_BIT32(12) // IN endpoint 12 interrupt
+#define STM32F4_OTGFS_DAINT_IEPINT11 BSP_BIT32(11) // IN endpoint 11 interrupt
+#define STM32F4_OTGFS_DAINT_IEPINT10 BSP_BIT32(10) // IN endpoint 10 interrupt
+#define STM32F4_OTGFS_DAINT_IEPINT9 BSP_BIT32(9) // IN endpoint 9 interrupt
+#define STM32F4_OTGFS_DAINT_IEPINT8 BSP_BIT32(8) // IN endpoint 8 interrupt
+#define STM32F4_OTGFS_DAINT_IEPINT7 BSP_BIT32(7) // IN endpoint 7 interrupt
+#define STM32F4_OTGFS_DAINT_IEPINT6 BSP_BIT32(6) // IN endpoint 6 interrupt
+#define STM32F4_OTGFS_DAINT_IEPINT5 BSP_BIT32(5) // IN endpoint 5 interrupt
+#define STM32F4_OTGFS_DAINT_IEPINT4 BSP_BIT32(4) // IN endpoint 4 interrupt
+#define STM32F4_OTGFS_DAINT_IEPINT3 BSP_BIT32(3) // IN endpoint 3 interrupt
+#define STM32F4_OTGFS_DAINT_IEPINT2 BSP_BIT32(2) // IN endpoint 2 interrupt
+#define STM32F4_OTGFS_DAINT_IEPINT1 BSP_BIT32(1) // IN endpoint 1 interrupt
+#define STM32F4_OTGFS_DAINT_IEPINT0 BSP_BIT32(0) // IN endpoint 0 interrupt
+
+ uint32_t daintmsk; // 0x81C
+#define STM32F4_OTGFS_DAINTMSK_OEPM(val) BSP_FLD32(val, 16, 31) // OUT endpoint interrupt mask
+#define STM32F4_OTGFS_DAINTMSK_OEPM_GET(reg) BSP_FLD32GET(reg, 16, 31)
+#define STM32F4_OTGFS_DAINTMSK_OEPM_SET(reg, val) BSP_FLD32SET(reg, val, 16, 31)
+#define STM32F4_OTGFS_DAINTMSK_IEPM(val) BSP_FLD32(val, 0, 15) // IN endpoint interrupt mask
+#define STM32F4_OTGFS_DAINTMSK_IEPM_GET(reg) BSP_FLD32GET(reg, 0, 15)
+#define STM32F4_OTGFS_DAINTMSK_IEPM_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15)
+
+ uint32_t unused5[2]; // 0x820 - 0x824
+
+ uint32_t dvbusdis; // 0x828
+#define STM32F4_OTGFS_DVBUSDIS_VBUSDT(val) BSP_FLD32(val, 0, 15) // Device Vbus discharge time
+#define STM32F4_OTGFS_DVBUSDIS_VBUSDT_GET(reg) BSP_FLD32GET(reg, 0, 15)
+#define STM32F4_OTGFS_DVBUSDIS_VBUSDT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15)
+
+ uint32_t dvbuspulse; // 0x82C
+#define STM32F4_OTGFS_DVBUSPULSE_DVBUSP(val) BSP_FLD32(val, 0, 15) // Device Vbus pulsing time
+#define STM32F4_OTGFS_DVBUSPULSE_DVBUSP_GET(reg) BSP_FLD32GET(reg, 0, 15)
+#define STM32F4_OTGFS_DVBUSPULSE_DVBUSP_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15)
+
+ uint32_t unused6; // 0x830
+
+ uint32_t diepempmsk; // 0x834
+#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM15 BSP_BIT32(15) // IN endpoint 15 TxFIFO empty interrupt mask
+#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM14 BSP_BIT32(14) // IN endpoint 14 TxFIFO empty interrupt mask
+#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM13 BSP_BIT32(13) // IN endpoint 13 TxFIFO empty interrupt mask
+#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM12 BSP_BIT32(12) // IN endpoint 12 TxFIFO empty interrupt mask
+#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM11 BSP_BIT32(11) // IN endpoint 11 TxFIFO empty interrupt mask
+#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM10 BSP_BIT32(10) // IN endpoint 10 TxFIFO empty interrupt mask
+#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM9 BSP_BIT32(9) // IN endpoint 9 TxFIFO empty interrupt mask
+#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM8 BSP_BIT32(8) // IN endpoint 8 TxFIFO empty interrupt mask
+#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM7 BSP_BIT32(7) // IN endpoint 7 TxFIFO empty interrupt mask
+#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM6 BSP_BIT32(6) // IN endpoint 6 TxFIFO empty interrupt mask
+#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM5 BSP_BIT32(5) // IN endpoint 5 TxFIFO empty interrupt mask
+#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM4 BSP_BIT32(4) // IN endpoint 4 TxFIFO empty interrupt mask
+#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM3 BSP_BIT32(3) // IN endpoint 3 TxFIFO empty interrupt mask
+#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM2 BSP_BIT32(2) // IN endpoint 2 TxFIFO empty interrupt mask
+#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM1 BSP_BIT32(1) // IN endpoint 1 TxFIFO empty interrupt mask
+#define STM32F4_OTGFS_DIEPEMPMSK_INEPTXFEM0 BSP_BIT32(0) // IN endpoint 0 TxFIFO empty interrupt mask
+
+} __attribute__ ((packed));
+typedef struct stm32f4_otgfs_dregs_s stm32f4_otgfs_dregs;
+
+struct stm32f4_otgfs_inepregs_s {
+ uint32_t diepctl; // 0x900
+#define STM32F4_OTGFS_DIEPCTL_EPENA BSP_BIT32(31) // Endpoint enable
+#define STM32F4_OTGFS_DIEPCTL_EPDIS BSP_BIT32(30) // Endpoint disable
+#define STM32F4_OTGFS_DIEPCTL_SODDFRM BSP_BIT32(29) // Set odd frame
+#define STM32F4_OTGFS_DIEPCTL_SD0PID BSP_BIT32(28) // Set DATA0 PID / Set even frame
+#define STM32F4_OTGFS_DIEPCTL_SEVNFRM BSP_BIT32(28) // Set DATA0 PID / Set even frame
+#define STM32F4_OTGFS_DIEPCTL_SNAK BSP_BIT32(27) // Set NAK
+#define STM32F4_OTGFS_DIEPCTL_CNAK BSP_BIT32(26) // Clear NAK
+#define STM32F4_OTGFS_DIEPCTL_TXFNUM(val) BSP_FLD32(val, 22, 25) // TxFIFO number
+#define STM32F4_OTGFS_DIEPCTL_TXFNUM_GET(reg) BSP_FLD32GET(reg, 22, 25)
+#define STM32F4_OTGFS_DIEPCTL_TXFNUM_SET(reg, val) BSP_FLD32SET(reg, val, 22, 25)
+#define STM32F4_OTGFS_DIEPCTL_STALL BSP_BIT32(21) // Stall handshake
+#define STM32F4_OTGFS_DIEPCTL_EPTYP(val) BSP_FLD32(val, 18, 19) // Endpoint type - 00 = Control, 01 = Isoch, 10 = Bulk, 11 = Interrupt
+#define STM32F4_OTGFS_DIEPCTL_EPTYP_GET(reg) BSP_FLD32GET(reg, 18, 19)
+#define STM32F4_OTGFS_DIEPCTL_EPTYP_SET(reg, val) BSP_FLD32SET(reg, val, 18, 19)
+#define EPTYPE_CTRL 0
+#define EPTYPE_ISOC 1
+#define EPTYPE_BULK 2
+#define EPTYPE_INTR 3
+#define STM32F4_OTGFS_DIEPCTL_NAKSTS BSP_BIT32(17) // NAK status
+#define STM32F4_OTGFS_DIEPCTL_EONUM_DPID BSP_BIT32(16) // Data PID / Even/odd frame
+#define STM32F4_OTGFS_DIEPCTL_USBAEP BSP_BIT32(15) // USB active endpoint
+#define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ(val) BSP_FLD32(val, 0, 1) // Maximum packet size (bytes)
+#define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ_GET(reg) BSP_FLD32GET(reg, 0, 1)
+#define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 1)
+#define EP0_MPSIZ_8 3
+#define EP0_MPSIZ_16 2
+#define EP0_MPSIZ_32 1
+#define EP0_MPSIZ_64 0
+#define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ_8 STM32F4_OTGFS_DIEPCTL_MPSIZ(EP0_MPSIZ_8)
+#define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ_16 STM32F4_OTGFS_DIEPCTL_MPSIZ(EP0_MPSIZ_16)
+#define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ_32 STM32F4_OTGFS_DIEPCTL_MPSIZ(EP0_MPSIZ_32)
+#define STM32F4_OTGFS_DIEPCTL_EP0_MPSIZ_64 STM32F4_OTGFS_DIEPCTL_MPSIZ(EP0_MPSIZ_64)
+#define STM32F4_OTGFS_DIEPCTL_MPSIZ(val) BSP_FLD32(val, 0, 10) // Maximum packet size (bytes)
+#define STM32F4_OTGFS_DIEPCTL_MPSIZ_GET(reg) BSP_FLD32GET(reg, 0, 10)
+#define STM32F4_OTGFS_DIEPCTL_MPSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 10)
+
+ uint32_t reserved_04;
+
+ uint32_t diepint; // 0x908
+#define STM32F4_OTGFS_DIEPINT_TXFE BSP_BIT32(7) // Transmit FIFO empty
+#define STM32F4_OTGFS_DIEPINT_INEPNE BSP_BIT32(6) // IN endpoint NAK effective
+#define STM32F4_OTGFS_DIEPINT_ITTXFE BSP_BIT32(4) // IN token received, TxFIFO empty
+#define STM32F4_OTGFS_DIEPINT_TOC BSP_BIT32(3) // Timeout condition
+#define STM32F4_OTGFS_DIEPINT_EPDISD BSP_BIT32(1) // Endpoint disabled
+#define STM32F4_OTGFS_DIEPINT_XFRC BSP_BIT32(0) // Transfer complete
+
+ uint32_t reserved_0C;
+
+ uint32_t dieptsiz; // 0x910
+#define STM32F4_OTGFS_DIEPTSIZ_EP0_PKTCNT(val) BSP_FLD32(val, 19, 20) // EP0 packet count
+#define STM32F4_OTGFS_DIEPTSIZ_EP0_PKTCNT_GET(reg) BSP_FLD32GET(reg, 19, 20)
+#define STM32F4_OTGFS_DIEPTSIZ_EP0_PKTCNT_SET(reg, val) BSP_FLD32SET(reg, val, 19, 20)
+#define STM32F4_OTGFS_DIEPTSIZ_EP0_XFRSIZ(val) BSP_FLD32(val, 0, 6) // EP0 transfer size
+#define STM32F4_OTGFS_DIEPTSIZ_EP0_XFRSIZ_GET(reg) BSP_FLD32GET(reg, 0, 6)
+#define STM32F4_OTGFS_DIEPTSIZ_EP0_XFRSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 6)
+#define STM32F4_OTGFS_DIEPTSIZ_MCNT(val) BSP_FLD32(val, 29, 30) // Multi count
+#define STM32F4_OTGFS_DIEPTSIZ_MCNT_GET(reg) BSP_FLD32GET(reg, 29, 30)
+#define STM32F4_OTGFS_DIEPTSIZ_MCNT_SET(reg, val) BSP_FLD32SET(reg, val, 29, 30)
+#define STM32F4_OTGFS_DIEPTSIZ_PKTCNT(val) BSP_FLD32(val, 19, 28) // Packet count
+#define STM32F4_OTGFS_DIEPTSIZ_PKTCNT_GET(reg) BSP_FLD32GET(reg, 19, 28)
+#define STM32F4_OTGFS_DIEPTSIZ_PKTCNT_SET(reg, val) BSP_FLD32SET(reg, val, 19, 28)
+#define STM32F4_OTGFS_DIEPTSIZ_XFRSIZ(val) BSP_FLD32(val, 0, 18) // Transfer size
+#define STM32F4_OTGFS_DIEPTSIZ_XFRSIZ_GET(reg) BSP_FLD32GET(reg, 0, 18)
+#define STM32F4_OTGFS_DIEPTSIZ_XFRSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 18)
+
+ uint32_t reserved_14;
+
+ uint32_t dtxfsts; // 0x918
+#define STM32F4_OTGFS_DTXFSTS_INEPTFSAV(val) BSP_FLD32(val, 0, 15) // IN endpoint TxFIFO space available
+#define STM32F4_OTGFS_DTXFSTS_INEPTFSAV_GET(reg) BSP_FLD32(reg, 0, 15)
+#define STM32F4_OTGFS_DTXFSTS_INEPTFSAV_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15)
+
+ uint32_t reserved_1C;
+
+} __attribute__ ((packed));
+typedef struct stm32f4_otgfs_inepregs_s stm32f4_otgfs_inepregs;
+
+struct stm32f4_otgfs_outepregs_s {
+ uint32_t doepctl; // 0xBx0: Endpoint control register
+#define STM32F4_OTGFS_DOEPCTL_EPENA BSP_BIT32(31) // Endpoint enable
+#define STM32F4_OTGFS_DOEPCTL_EPDIS BSP_BIT32(30) // Endpoint disable
+#define STM32F4_OTGFS_DOEPCTL_SD1PID BSP_BIT32(29) // Set DATA1 PID / Set odd frame
+#define STM32F4_OTGFS_DOEPCTL_SD0PID BSP_BIT32(28) // Set DATA0 PID / Set even frame
+#define STM32F4_OTGFS_DOEPCTL_SNAK BSP_BIT32(27) // Set NAK
+#define STM32F4_OTGFS_DOEPCTL_CNAK BSP_BIT32(26) // Clear NAK
+#define STM32F4_OTGFS_DOEPCTL_STALL BSP_BIT32(21) // Stall handshake
+#define STM32F4_OTGFS_DOEPCTL_SNPM BSP_BIT32(20) // Snoop mode
+#define STM32F4_OTGFS_DOEPCTL_EPTYP(val) BSP_FLD32(val, 18, 19) // Endpoint type - 00 = Control, 01 = Isoch, 10 = Bulk, 11 = Interrupt
+#define STM32F4_OTGFS_DOEPCTL_EPTYP_GET(reg) BSP_FLD32GET(reg, 18, 19)
+#define STM32F4_OTGFS_DOEPCTL_EPTYP_SET(reg, val) BSP_FLD32SET(reg, val, 18, 19)
+#define STM32F4_OTGFS_DOEPCTL_NAKSTS BSP_BIT32(17) // NAK status
+#define STM32F4_OTGFS_DOEPCTL_EONUM_DPID BSP_BIT32(16) // Data PID / Even/odd frame
+#define STM32F4_OTGFS_DOEPCTL_USBAEP BSP_BIT32(15) // USB active endpoint
+#define STM32F4_OTGFS_DOEPCTL_MPSIZ(val) BSP_FLD32(val, 0, 10) // Maximum packet size (bytes)
+#define STM32F4_OTGFS_DOEPCTL_MPSIZ_GET(reg) BSP_FLD32GET(reg, 0, 10)
+#define STM32F4_OTGFS_DOEPCTL_MPSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 10)
+
+ uint32_t resv04;
+
+ uint32_t doepint; // 0xBx8: Endpoint interrupt register
+#define STM32F4_OTGFS_DOEPINT_B2BSTUP BSP_BIT32(6) // Back-to-back SETUP packets received
+#define STM32F4_OTGFS_DOEPINT_OTEPDIS BSP_BIT32(4) // OUT token received when endpoint disabled
+#define STM32F4_OTGFS_DOEPINT_STUP BSP_BIT32(3) // SETUP phase done
+#define STM32F4_OTGFS_DOEPINT_EPDISD BSP_BIT32(1) // Endpoint disabled interrupt
+#define STM32F4_OTGFS_DOEPINT_XFRC BSP_BIT32(0) // Transfer complete
+
+ uint32_t doeptsiz; // 0xBy0
+#define STM32F4_OTGFS_DOEPTSIZ_EP0_STUPCNT(val) BSP_FLD32(val, 29, 30) // EP0 SETUP packet count
+#define STM32F4_OTGFS_DOEPTSIZ_EP0_STUPCNT_GET(reg) BSP_FLD32GET(reg, 29, 30)
+#define STM32F4_OTGFS_DOEPTSIZ_EP0_STUPCNT_SET(reg, val) BSP_FLD32SET(reg, val, 29, 30)
+#define STM32F4_OTGFS_DOEPTSIZ_EP0_PKTCNT BSP_BIT32(19) // EP0 packet count
+#define STM32F4_OTGFS_DOEPTSIZ_EP0_XFRSIZ(val) BSP_FLD32(val, 0, 6) // EP0 transfer size
+#define STM32F4_OTGFS_DOEPTSIZ_EP0_XFRSIZ_GET(reg) BSP_FLD32GET(reg, 0, 6)
+#define STM32F4_OTGFS_DOEPTSIZ_EP0_XFRSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 6)
+#define STM32F4_OTGFS_DOEPTSIZ_RXDPID(val) BSP_FLD32(val, 29, 30) // Received data PID
+#define STM32F4_OTGFS_DOEPTSIZ_RXDPID_GET(reg) BSP_FLD32GET(reg, 29, 30)
+#define STM32F4_OTGFS_DOEPTSIZ_RXDPID_SET(reg, val) BSP_FLD32SET(reg, val, 29, 30)
+#define STM32F4_OTGFS_DOEPTSIZ_PKTCNT(val) BSP_FLD32(val, 19, 28) // Packet count
+#define STM32F4_OTGFS_DOEPTSIZ_PKTCNT_GET(reg) BSP_FLD32GET(reg, 19, 28)
+#define STM32F4_OTGFS_DOEPTSIZ_PKTCNT_SET(reg, val) BSP_FLD32SET(reg, val, 19, 28)
+#define STM32F4_OTGFS_DOEPTSIZ_XFRSIZ(val) BSP_FLD32(val, 0, 18) // Transfer size
+#define STM32F4_OTGFS_DOEPTSIZ_XFRSIZ_GET(reg) BSP_FLD32GET(reg, 0, 18)
+#define STM32F4_OTGFS_DOEPTSIZ_XFRSIZ_SET(reg, val) BSP_FLD32SET(reg, val, 0, 18)
+
+ uint32_t resv14[3];
+} __attribute__ ((packed));
+typedef struct stm32f4_otgfs_outepregs_s stm32f4_otgfs_outepregs;
+
+struct stm32f4_otgfs_pwrctlregs_s {
+ uint32_t pcgcctl; // 0xE00: Power and clock gating control register
+#define STM32F4_OTGFS_PCGCCTL_PHYSUSP BSP_BIT32(4) // PHY suspend
+#define STM32F4_OTGFS_PCGCCTL_GATEHCLK BSP_BIT32(1) // Gate HCLK
+#define STM32F4_OTGFS_PCGCCTL_STPPCLK BSP_BIT32(0) // Stop PHY clk
+} __attribute__ ((packed));
+typedef struct stm32f4_otgfs_pwrctlregs_s stm32f4_otgfs_pwrctlregs;
+
+#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_OTGFS_H */
--
1.8.4.2
>From ff6c2f21e545c42dfb9e3687e4d78a01a684132a Mon Sep 17 00:00:00 2001
From: Chris Nott <chrisn at vl.com.au>
Date: Mon, 3 Mar 2014 03:33:18 -0800
Subject: [PATCH 6/8] Added USB OTG register definitions to build. Changed RCC
init to use build clock definitions
---
c/src/lib/libbsp/arm/stm32f4/Makefile.am | 1 +
c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h | 10 ++++++++
c/src/lib/libbsp/arm/stm32f4/preinstall.am | 4 ++++
c/src/lib/libbsp/arm/stm32f4/startup/rcc.c | 33 ++++++++++++++++++++------
4 files changed, 41 insertions(+), 7 deletions(-)
diff --git a/c/src/lib/libbsp/arm/stm32f4/Makefile.am b/c/src/lib/libbsp/arm/stm32f4/Makefile.am
index 4ea4334..e2fdc62 100644
--- a/c/src/lib/libbsp/arm/stm32f4/Makefile.am
+++ b/c/src/lib/libbsp/arm/stm32f4/Makefile.am
@@ -57,6 +57,7 @@ include_bsp_HEADERS += include/stm32f4xxxx_pwr.h
include_bsp_HEADERS += include/stm32f4xxxx_syscfg.h
include_bsp_HEADERS += include/stm32f4xxxx_tim.h
include_bsp_HEADERS += include/stm32f4xxxx_flash.h
+include_bsp_HEADERS += include/stm32f4xxxx_otgfs.h
include_bsp_HEADERS += include/stm32_i2c.h
include_bsp_HEADERS += include/i2c.h
include_bsp_HEADERS += include/stm32_usart.h
diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
index 8272a2d..405bb48 100755
--- a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
+++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
@@ -74,6 +74,16 @@
#define STM32F4_TIM13 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x1c00))
#define STM32F4_TIM14 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x2000))
+#include <bsp/stm32f4xxxx_otgfs.h>
+#define STM32F4_OTGFS_BASE (STM32F4_AHB2_BASE + 0x0000)
+#define STM32F4_OTGFS_CORE ((volatile stm32f4_otgfs *) (STM32F4_OTGFS_BASE + 0x000))
+#define STM32F4_OTGFS_DEV ((volatile stm32f4_otgfs_dregs *) (STM32F4_OTGFS_BASE + 0x800))
+#define STM32F4_OTGFS_INEP ((volatile stm32f4_otgfs_inepregs *) (STM32F4_OTGFS_BASE + 0x900))
+#define STM32F4_OTGFS_OUTEP ((volatile stm32f4_otgfs_outepregs *) (STM32F4_OTGFS_BASE + 0xb00))
+#define STM32F4_OTGFS_PWRCTL ((volatile stm32f4_otgfs_pwrctlregs *) (STM32F4_OTGFS_BASE + 0xe00))
+
+#define STM32F4_OTGFS_FIFO_BASE (STM32F4_OTGFS_BASE + USB_FIFO_BASE)
+
#endif /* STM32F4_FAMILY_F4XXXX */
#ifdef STM32F4_FAMILY_F10XXX
diff --git a/c/src/lib/libbsp/arm/stm32f4/preinstall.am b/c/src/lib/libbsp/arm/stm32f4/preinstall.am
index 61f4549..40fdc7f 100644
--- a/c/src/lib/libbsp/arm/stm32f4/preinstall.am
+++ b/c/src/lib/libbsp/arm/stm32f4/preinstall.am
@@ -145,6 +145,10 @@ $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_flash.h: include/stm32f4xxxx_flash.h $(PROJEC
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_flash.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_flash.h
+$(PROJECT_INCLUDE)/bsp/stm32f4xxxx_otgfs.h: include/stm32f4xxxx_otgfs.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_otgfs.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_otgfs.h
+
$(PROJECT_INCLUDE)/bsp/stm32_i2c.h: include/stm32_i2c.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32_i2c.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32_i2c.h
diff --git a/c/src/lib/libbsp/arm/stm32f4/startup/rcc.c b/c/src/lib/libbsp/arm/stm32f4/startup/rcc.c
index 47ada3f..20508fb 100755
--- a/c/src/lib/libbsp/arm/stm32f4/startup/rcc.c
+++ b/c/src/lib/libbsp/arm/stm32f4/startup/rcc.c
@@ -17,6 +17,13 @@
#include <rtems.h>
+
+#if ((STM32F4_HSE_OSCILLATOR == 8000000) \
+ && (STM32F4_HCLK == 168000000) \
+ && (STM32F4_SYSCLK == 168000000) \
+ && (STM32F4_PCLK1 == 42000000) \
+ && (STM32F4_PCLK2 == 84000000))
+
/*
*=============================================================================
* Supported STM32F4xx device revision | Rev A
@@ -55,7 +62,7 @@
*-----------------------------------------------------------------------------
* Flash Latency(WS) | 5
*-----------------------------------------------------------------------------
- * Prefetch Buffer | OFF
+ * Prefetch Buffer | ON
*-----------------------------------------------------------------------------
* Instruction cache | ON
*-----------------------------------------------------------------------------
@@ -94,12 +101,12 @@ stm32f4_rcc_init (void)
// Enable HSE
rcc->cr |= STM32F4_RCC_CR_HSEON;
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- hserdy = rcc->cr & STM32F4_RCC_CR_HSERDY;
- cnt++;
- } while (!hserdy && (cnt < 2000));
+ /* Wait till HSE is ready and if Time out is reached exit */
+ do
+ {
+ hserdy = rcc->cr & STM32F4_RCC_CR_HSERDY;
+ cnt++;
+ } while (!hserdy && (cnt < 2000));
if (!hserdy)
{
@@ -162,6 +169,18 @@ stm32f4_rcc_init (void)
}
}
+#else
+
+#warning STM32F4: Unrecognised clock configuration, using default clock mode.
+
+void
+stm32f4_rcc_init (void)
+{
+}
+
+#endif
+
+
static void rcc_set(
stm32f4_rcc_index index,
bool set,
--
1.8.4.2
>From 3e494adc3ad44622610ea4a237b8c23e167114df Mon Sep 17 00:00:00 2001
From: Chris Nott <chrisn at vl.com.au>
Date: Fri, 4 Apr 2014 03:48:27 -0700
Subject: [PATCH 7/8] Added STM32F4 ADC definitions
---
c/src/lib/libbsp/arm/stm32f4/Makefile.am | 1 +
c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h | 6 +
.../libbsp/arm/stm32f4/include/stm32f4xxxx_adc.h | 320 +++++++++++++++++++++
c/src/lib/libbsp/arm/stm32f4/preinstall.am | 4 +
4 files changed, 331 insertions(+)
create mode 100755 c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_adc.h
diff --git a/c/src/lib/libbsp/arm/stm32f4/Makefile.am b/c/src/lib/libbsp/arm/stm32f4/Makefile.am
index e2fdc62..2634ec5 100644
--- a/c/src/lib/libbsp/arm/stm32f4/Makefile.am
+++ b/c/src/lib/libbsp/arm/stm32f4/Makefile.am
@@ -50,6 +50,7 @@ include_bsp_HEADERS += include/stm32f4.h
include_bsp_HEADERS += include/stm32f10xxx_gpio.h
include_bsp_HEADERS += include/stm32f10xxx_rcc.h
include_bsp_HEADERS += include/stm32f10xxx_exti.h
+include_bsp_HEADERS += include/stm32f4xxxx_adc.h
include_bsp_HEADERS += include/stm32f4xxxx_exti.h
include_bsp_HEADERS += include/stm32f4xxxx_gpio.h
include_bsp_HEADERS += include/stm32f4xxxx_rcc.h
diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
index 405bb48..676542c 100755
--- a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
+++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4.h
@@ -74,6 +74,12 @@
#define STM32F4_TIM13 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x1c00))
#define STM32F4_TIM14 ((volatile stm32f4_tim *) (STM32F4_APB1_BASE + 0x2000))
+#include <bsp/stm32f4xxxx_adc.h>
+#define STM32F4_ADC1 ((volatile stm32f4_adc_chan *) (STM32F4_APB2_BASE + 0x2000))
+#define STM32F4_ADC2 ((volatile stm32f4_adc_chan *) (STM32F4_APB2_BASE + 0x2100))
+#define STM32F4_ADC3 ((volatile stm32f4_adc_chan *) (STM32F4_APB2_BASE + 0x2200))
+#define STM32F4_ADC_COMMON ((volatile stm32f4_adc_com *) (STM32F4_APB2_BASE + 0x2300))
+
#include <bsp/stm32f4xxxx_otgfs.h>
#define STM32F4_OTGFS_BASE (STM32F4_AHB2_BASE + 0x0000)
#define STM32F4_OTGFS_CORE ((volatile stm32f4_otgfs *) (STM32F4_OTGFS_BASE + 0x000))
diff --git a/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_adc.h b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_adc.h
new file mode 100755
index 0000000..c1e28f9
--- /dev/null
+++ b/c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_adc.h
@@ -0,0 +1,320 @@
+/*
+ * Copyright (c) 2014 Chris Nott. All rights reserved.
+ *
+ * Virtual Logic
+ * 21-25 King St.
+ * Rockdale NSW 2216
+ * Australia
+ * <rtems at vl.com.au>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_ADC_H
+#define LIBBSP_ARM_STM32F4_STM32F4XXXX_ADC_H
+
+#include <bsp/utility.h>
+
+struct stm32f4_adc_chan_s {
+ uint32_t sr; // 0x00: Status register
+#define STM32F4_ADC_SR_OVR BSP_BIT32(5) // Overrun
+#define STM32F4_ADC_SR_STRT BSP_BIT32(4) // Regular channel start flag
+#define STM32F4_ADC_SR_JSTRT BSP_BIT32(3) // Injected channel start flag
+#define STM32F4_ADC_SR_JEOC BSP_BIT32(2) // Injected channel end of conversion
+#define STM32F4_ADC_SR_EOC BSP_BIT32(1) // Regular channel end of conversion
+#define STM32F4_ADC_SR_AWD BSP_BIT32(0) // Analog watchdog flag
+
+ uint32_t cr1; // 0x04: Control register 1
+#define STM32F4_ADC_CR1_OVRIE BSP_BIT32(26) // Overrun interrupt enable
+#define STM32F4_ADC_CR1_RES(val) BSP_FLD32(val, 24, 25) // Resolution
+#define STM32F4_ADC_CR1_RES_GET(reg) BSP_FLD32GET(reg, 24, 25)
+#define STM32F4_ADC_CR1_RES_SET(reg, val) BSP_FLD32SET(reg, val, 24, 25)
+#define ADC_CR1_RES_12BIT 0
+#define ADC_CR1_RES_10BIT 1
+#define ADC_CR1_RES_8BIT 2
+#define ADC_CR1_RES_6BIT 3
+#define STM32F4_ADC_CR1_AWDEN BSP_BIT32(23) // Analog watchdog enable on regular channels
+#define STM32F4_ADC_CR1_JAWDEN BSP_BIT32(22) // Analog watchdog enable on injected channels
+#define STM32F4_ADC_CR1_DISCNUM(val) BSP_FLD32(val, 13, 15) // Discontinuous mode channel count
+#define STM32F4_ADC_CR1_DISCNUM_GET(reg) BSP_FLD32GET(reg, 13, 15)
+#define STM32F4_ADC_CR1_DISCNUM_SET(reg, val) BSP_FLD32SET(reg, val, 13, 15)
+#define STM32F4_ADC_CR1_JDISCEN BSP_BIT32(12) // Discontinous mode on injected channels
+#define STM32F4_ADC_CR1_DISCEN BSP_BIT32(11) // Discontinous mode on regular channels
+#define STM32F4_ADC_CR1_JAUTO BSP_BIT32(10) // Automated injected group conversion
+#define STM32F4_ADC_CR1_AWDSGL BSP_BIT32(9) // Enable watchdog on single channel in scan mode
+#define STM32F4_ADC_CR1_SCAN BSP_BIT32(8) // Scan mode
+#define STM32F4_ADC_CR1_JEOCIE BSP_BIT32(7) // Interrupt enable for injected channels
+#define STM32F4_ADC_CR1_AWDIE BSP_BIT32(6) // Analog watchdog interrupt enable
+#define STM32F4_ADC_CR1_EOCIE BSP_BIT32(5) // Interrupt enable for EOC
+#define STM32F4_ADC_CR1_AWDCH(val) BSP_FLD32(val, 0, 4) // Analog watchdog channel select bits
+#define STM32F4_ADC_CR1_AWDCH_GET(reg) BSP_FLD32GET(reg, 0, 4)
+#define STM32F4_ADC_CR1_AWDCH_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
+
+ uint32_t cr2; // 0x08: Control register 2
+#define STM32F4_ADC_CR2_SWSTART BSP_BIT32(30) // Start conversion of regular channels
+#define STM32F4_ADC_CR2_EXTEN(val) BSP_FLD32(val, 28, 29) // External trigger enable for regular channels
+#define STM32F4_ADC_CR2_EXTEN_GET(reg) BSP_FLD32GET(reg, 28, 29)
+#define STM32F4_ADC_CR2_EXTEN_SET(reg, val) BSP_FLD32SET(reg, val, 28, 29)
+#define STM32F4_ADC_CR2_JEXTEN(val) BSP_FLD32(val, 20, 21) // External trigger enable for injected channels
+#define STM32F4_ADC_CR2_JEXTEN_GET(reg) BSP_FLD32GET(reg, 20, 21)
+#define STM32F4_ADC_CR2_JEXTEN_SET(reg, val) BSP_FLD32SET(reg, val, 20, 21)
+#define ADC_CR2_TRIGGER_DISABLE 0
+#define ADC_CR2_TRIGGER_RISING 1
+#define ADC_CR2_TRIGGER_FALLING 2
+#define ADC_CR2_TRIGGER_BOTH 3
+#define STM32F4_ADC_CR2_EXTSEL(val) BSP_FLD32(val, 24, 27) // External event select for regular group
+#define STM32F4_ADC_CR2_EXTSEL_GET(reg) BSP_FLD32GET(reg, 24, 27)
+#define STM32F4_ADC_CR2_EXTSEL_SET(reg, val) BSP_FLD32SET(reg, val, 24, 27)
+#define ADC_CR2_EVT_TIMER1_CC1 0x0
+#define ADC_CR2_EVT_TIMER1_CC2 0x1
+#define ADC_CR2_EVT_TIMER1_CC3 0x2
+#define ADC_CR2_EVT_TIMER2_CC2 0x3
+#define ADC_CR2_EVT_TIMER2_CC3 0x4
+#define ADC_CR2_EVT_TIMER2_CC4 0x5
+#define ADC_CR2_EVT_TIMER2_TRGO 0x6
+#define ADC_CR2_EVT_TIMER3_CC1 0x7
+#define ADC_CR2_EVT_TIMER3_TRGO 0x8
+#define ADC_CR2_EVT_TIMER4_CC1 0x9
+#define ADC_CR2_EVT_TIMER5_CC1 0xa
+#define ADC_CR2_EVT_TIMER5_CC2 0xb
+#define ADC_CR2_EVT_TIMER5_CC3 0xc
+#define ADC_CR2_EVT_TIMER8_CC1 0xd
+#define ADC_CR2_EVT_TIMER8_TRGO 0xe
+#define ADC_CR2_EVT_EXTI_11 0xf
+#define STM32F4_ADC_CR2_JSWSTART BSP_BIT32(22) // Start conversion of injected channels
+#define STM32F4_ADC_CR2_JEXTSEL(val) BSP_FLD32(val, 16, 19) // External event select for injected group
+#define STM32F4_ADC_CR2_JEXTSEL_GET(reg) BSP_FLD32GET(reg, 16, 19)
+#define STM32F4_ADC_CR2_JEXTSEL_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19)
+#define ADC_CR2_JEVT_TIMER1_CC4 0x0
+#define ADC_CR2_JEVT_TIMER1_TRGO 0x1
+#define ADC_CR2_JEVT_TIMER2_CC1 0x2
+#define ADC_CR2_JEVT_TIMER2_TRGO 0x3
+#define ADC_CR2_JEVT_TIMER3_CC2 0x4
+#define ADC_CR2_JEVT_TIMER3_CC4 0x5
+#define ADC_CR2_JEVT_TIMER4_CC1 0x6
+#define ADC_CR2_JEVT_TIMER4_CC2 0x7
+#define ADC_CR2_JEVT_TIMER4_CC3 0x8
+#define ADC_CR2_JEVT_TIMER4_TRGO 0x9
+#define ADC_CR2_JEVT_TIMER5_CC4 0xa
+#define ADC_CR2_JEVT_TIMER5_TRGO 0xb
+#define ADC_CR2_JEVT_TIMER8_CC2 0xc
+#define ADC_CR2_JEVT_TIMER8_CC3 0xd
+#define ADC_CR2_JEVT_TIMER8_CC4 0xe
+#define ADC_CR2_JEVT_EXTI_15 0xf
+#define STM32F4_ADC_CR2_ALIGN BSP_BIT32(11) // Data alignment
+#define STM32F4_ADC_CR2_ALIGN_RIGHT 0
+#define STM32F4_ADC_CR2_ALIGN_LEFT STM32F4_ADC_CR2_ALIGN
+#define STM32F4_ADC_CR2_EOCS BSP_BIT32(10) // End of conversion selection
+#define STM32F4_ADC_CR2_DDS BSP_BIT32(9) // DMA disable selection (single ADC mode)
+#define STM32F4_ADC_CR2_DMA BSP_BIT32(8) // DMA access mode (single ADC)
+#define STM32F4_ADC_CR2_CONT BSP_BIT32(1) // Continuous conversion
+#define STM32F4_ADC_CR2_ADON BSP_BIT32(0) // A/D converter ON
+
+ uint32_t smpr1; // 0x0C: Sample time register 1
+#define ADC_SAMPLE_3CYCLE 0
+#define ADC_SAMPLE_15CYCLE 1
+#define ADC_SAMPLE_28CYCLE 2
+#define ADC_SAMPLE_56CYCLE 3
+#define ADC_SAMPLE_84CYCLE 4
+#define ADC_SAMPLE_112CYCLE 5
+#define ADC_SAMPLE_144CYCLE 6
+#define ADC_SAMPLE_480CYCLE 7
+#define STM32F4_ADC_SMP18(val) BSP_FLD32(val, 24, 26) // Channel 18 sampling time selection
+#define STM32F4_ADC_SMP18_GET(reg) BSP_FLD32GET(reg, 24, 26)
+#define STM32F4_ADC_SMP18_SET(reg, val) BSP_FLD32SET(reg, val, 24, 26)
+#define STM32F4_ADC_SMP17(val) BSP_FLD32(val, 21, 23) // Channel 17 sampling time selection
+#define STM32F4_ADC_SMP17_GET(reg) BSP_FLD32GET(reg, 21, 23)
+#define STM32F4_ADC_SMP17_SET(reg, val) BSP_FLD32SET(reg, val, 21, 23)
+#define STM32F4_ADC_SMP16(val) BSP_FLD32(val, 18, 20) // Channel 16 sampling time selection
+#define STM32F4_ADC_SMP16_GET(reg) BSP_FLD32GET(reg, 18, 20)
+#define STM32F4_ADC_SMP16_SET(reg, val) BSP_FLD32SET(reg, val, 18, 20)
+#define STM32F4_ADC_SMP15(val) BSP_FLD32(val, 15, 17) // Channel 15 sampling time selection
+#define STM32F4_ADC_SMP15_GET(reg) BSP_FLD32GET(reg, 15, 17)
+#define STM32F4_ADC_SMP15_SET(reg, val) BSP_FLD32SET(reg, val, 15, 17)
+#define STM32F4_ADC_SMP14(val) BSP_FLD32(val, 12, 14) // Channel 14 sampling time selection
+#define STM32F4_ADC_SMP14_GET(reg) BSP_FLD32GET(reg, 12, 14)
+#define STM32F4_ADC_SMP14_SET(reg, val) BSP_FLD32SET(reg, val, 12, 14)
+#define STM32F4_ADC_SMP13(val) BSP_FLD32(val, 9, 11) // Channel 13 sampling time selection
+#define STM32F4_ADC_SMP13_GET(reg) BSP_FLD32GET(reg, 9, 11)
+#define STM32F4_ADC_SMP13_SET(reg, val) BSP_FLD32SET(reg, val, 9, 11)
+#define STM32F4_ADC_SMP12(val) BSP_FLD32(val, 6, 8) // Channel 12 sampling time selection
+#define STM32F4_ADC_SMP12_GET(reg) BSP_FLD32GET(reg, 6, 8)
+#define STM32F4_ADC_SMP12_SET(reg, val) BSP_FLD32SET(reg, val, 6, 8)
+#define STM32F4_ADC_SMP11(val) BSP_FLD32(val, 3, 5) // Channel 11 sampling time selection
+#define STM32F4_ADC_SMP11_GET(reg) BSP_FLD32GET(reg, 3, 5)
+#define STM32F4_ADC_SMP11_SET(reg, val) BSP_FLD32SET(reg, val, 3, 5)
+#define STM32F4_ADC_SMP10(val) BSP_FLD32(val, 0, 2) // Channel 10 sampling time selection
+#define STM32F4_ADC_SMP10_GET(reg) BSP_FLD32GET(reg, 0, 2)
+#define STM32F4_ADC_SMP10_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2)
+
+ uint32_t smpr2; // 0x10: Sample time register 2
+#define STM32F4_ADC_SMP9(val) BSP_FLD32(val, 27, 29) // Channel 9 sampling time selection
+#define STM32F4_ADC_SMP9_GET(reg) BSP_FLD32GET(reg, 27, 29)
+#define STM32F4_ADC_SMP9_SET(reg, val) BSP_FLD32SET(reg, val, 27, 29)
+#define STM32F4_ADC_SMP8(val) BSP_FLD32(val, 24, 26) // Channel 8 sampling time selection
+#define STM32F4_ADC_SMP8_GET(reg) BSP_FLD32GET(reg, 24, 26)
+#define STM32F4_ADC_SMP8_SET(reg, val) BSP_FLD32SET(reg, val, 24, 26)
+#define STM32F4_ADC_SMP7(val) BSP_FLD32(val, 21, 23) // Channel 7 sampling time selection
+#define STM32F4_ADC_SMP7_GET(reg) BSP_FLD32GET(reg, 21, 23)
+#define STM32F4_ADC_SMP7_SET(reg, val) BSP_FLD32SET(reg, val, 21, 23)
+#define STM32F4_ADC_SMP6(val) BSP_FLD32(val, 18, 20) // Channel 6 sampling time selection
+#define STM32F4_ADC_SMP6_GET(reg) BSP_FLD32GET(reg, 18, 20)
+#define STM32F4_ADC_SMP6_SET(reg, val) BSP_FLD32SET(reg, val, 18, 20)
+#define STM32F4_ADC_SMP5(val) BSP_FLD32(val, 15, 17) // Channel 5 sampling time selection
+#define STM32F4_ADC_SMP5_GET(reg) BSP_FLD32GET(reg, 15, 17)
+#define STM32F4_ADC_SMP5_SET(reg, val) BSP_FLD32SET(reg, val, 15, 17)
+#define STM32F4_ADC_SMP4(val) BSP_FLD32(val, 12, 14) // Channel 4 sampling time selection
+#define STM32F4_ADC_SMP4_GET(reg) BSP_FLD32GET(reg, 12, 14)
+#define STM32F4_ADC_SMP4_SET(reg, val) BSP_FLD32SET(reg, val, 12, 14)
+#define STM32F4_ADC_SMP3(val) BSP_FLD32(val, 9, 11) // Channel 3 sampling time selection
+#define STM32F4_ADC_SMP3_GET(reg) BSP_FLD32GET(reg, 9, 11)
+#define STM32F4_ADC_SMP3_SET(reg, val) BSP_FLD32SET(reg, val, 9, 11)
+#define STM32F4_ADC_SMP2(val) BSP_FLD32(val, 6, 8) // Channel 2 sampling time selection
+#define STM32F4_ADC_SMP2_GET(reg) BSP_FLD32GET(reg, 6, 8)
+#define STM32F4_ADC_SMP2_SET(reg, val) BSP_FLD32SET(reg, val, 6, 8)
+#define STM32F4_ADC_SMP1(val) BSP_FLD32(val, 3, 5) // Channel 1 sampling time selection
+#define STM32F4_ADC_SMP1_GET(reg) BSP_FLD32GET(reg, 3, 5)
+#define STM32F4_ADC_SMP1_SET(reg, val) BSP_FLD32SET(reg, val, 3, 5)
+#define STM32F4_ADC_SMP0(val) BSP_FLD32(val, 0, 2) // Channel 0 sampling time selection
+#define STM32F4_ADC_SMP0_GET(reg) BSP_FLD32GET(reg, 0, 2)
+#define STM32F4_ADC_SMP0_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2)
+
+ uint32_t jofr[4]; // 0x14-0x20: Injected channel data offset registers
+#define STM32F4_ADC_JOFFSET(val) BSP_FLD32(val, 0, 11) // Data offset for injected channel
+#define STM32F4_ADC_JOFFSET_GET(reg) BSP_FLD32GET(reg, 0, 11)
+#define STM32F4_ADC_JOFFSET_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11)
+
+ uint32_t htr; // 0x24: Watchdog higher threshold register
+#define STM32F4_ADC_HT(val) BSP_FLD32(val, 0, 11) // Analog watchdog higher threshold
+#define STM32F4_ADC_HT_GET(reg) BSP_FLD32GET(reg, 0, 11)
+#define STM32F4_ADC_HT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11)
+
+ uint32_t ltr; // 0x28: Watchdog lower threshold register
+#define STM32F4_ADC_LT(val) BSP_FLD32(val, 0, 11) // Analog watchdog lower threshold
+#define STM32F4_ADC_LT_GET(reg) BSP_FLD32GET(reg, 0, 11)
+#define STM32F4_ADC_LT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11)
+
+ uint32_t sqr[3]; // 0x2c-0x34: Regular sequence registers
+#define STM32F4_ADC_SQR_L(val) BSP_FLD32(val, 20, 23) // Regular channel sequence length
+#define STM32F4_ADC_SQR_L_GET(reg) BSP_FLD32GET(reg, 20, 23)
+#define STM32F4_ADC_SQR_L_SET(reg, val) BSP_FLD32SET(reg, val, 20, 23)
+
+ uint32_t jsqr; // 0x38: Injected sequence register
+#define STM32F4_ADC_JSQR_JL(val) BSP_FLD32(val, 20, 21) // Injected sequence length
+#define STM32F4_ADC_JSQR_JL_GET(reg) BSP_FLD32GET(reg, 20, 21)
+#define STM32F4_ADC_JSQR_JL_SET(reg, val) BSP_FLD32SET(reg, val, 20, 21)
+#define STM32F4_ADC_JSQR_JSQ4(val) BSP_FLD32(val, 15, 19) // 4th conversion in injected sequence
+#define STM32F4_ADC_JSQR_JSQ4_GET(reg) BSP_FLD32GET(reg, 15, 19)
+#define STM32F4_ADC_JSQR_JSQ4_SET(reg, val) BSP_FLD32SET(reg, val, 15, 19)
+#define STM32F4_ADC_JSQR_JSQ3(val) BSP_FLD32(val, 10, 14) // 3rd conversion in injected sequence
+#define STM32F4_ADC_JSQR_JSQ3_GET(reg) BSP_FLD32GET(reg, 10, 14)
+#define STM32F4_ADC_JSQR_JSQ3_SET(reg, val) BSP_FLD32SET(reg, val, 10, 14)
+#define STM32F4_ADC_JSQR_JSQ2(val) BSP_FLD32(val, 5, 9) // 2nd conversion in injected sequence
+#define STM32F4_ADC_JSQR_JSQ2_GET(reg) BSP_FLD32GET(reg, 5, 9)
+#define STM32F4_ADC_JSQR_JSQ2_SET(reg, val) BSP_FLD32SET(reg, val, 5, 9)
+#define STM32F4_ADC_JSQR_JSQ1(val) BSP_FLD32(val, 0, 4) // 1st conversion in injected sequence
+#define STM32F4_ADC_JSQR_JSQ1_GET(reg) BSP_FLD32GET(reg, 0, 4)
+#define STM32F4_ADC_JSQR_JSQ1_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
+
+ uint32_t jdr[4]; // 0x3c-0x48: Injected data registers
+#define STM32F4_ADC_JDATA(val) BSP_FLD32(val, 0, 15) // Injected data
+#define STM32F4_ADC_JDATA_GET(reg) BSP_FLD32GET(reg, 0, 15)
+#define STM32F4_ADC_JDATA_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15)
+
+ uint32_t dr; // 0x4c: Regular data register
+#define STM32F4_ADC_DATA(val) BSP_FLD32(val, 0, 15) // Regular data
+#define STM32F4_ADC_DATA_GET(reg) BSP_FLD32GET(reg, 0, 15)
+#define STM32F4_ADC_DATA_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15)
+
+} __attribute__ ((packed));
+typedef struct stm32f4_adc_chan_s stm32f4_adc_chan;
+
+struct stm32f4_adc_com_s {
+ uint32_t csr; // 0x00: Common status register
+#define STM32F4_ADC_CSR_OVR3 BSP_BIT32(21) // Overrun flag ADC3
+#define STM32F4_ADC_CSR_STRT3 BSP_BIT32(20) // Regular start flag ADC3
+#define STM32F4_ADC_CSR_JSTRT3 BSP_BIT32(19) // Injected start flag ADC3
+#define STM32F4_ADC_CSR_JEOC3 BSP_BIT32(18) // Injected channel end of conversion flag ADC3
+#define STM32F4_ADC_CSR_EOC3 BSP_BIT32(17) // Channel end of conversion flag ADC3
+#define STM32F4_ADC_CSR_AWD3 BSP_BIT32(16) // Analog watchdog flag ADC3
+#define STM32F4_ADC_CSR_OVR2 BSP_BIT32(13) // Overrun flag ADC2
+#define STM32F4_ADC_CSR_STRT2 BSP_BIT32(12) // Regular start flag ADC2
+#define STM32F4_ADC_CSR_JSTRT2 BSP_BIT32(11) // Injected start flag ADC2
+#define STM32F4_ADC_CSR_JEOC2 BSP_BIT32(10) // Injected channel end of conversion flag ADC2
+#define STM32F4_ADC_CSR_EOC2 BSP_BIT32(9) // Channel end of conversion flag ADC2
+#define STM32F4_ADC_CSR_AWD2 BSP_BIT32(8) // Analog watchdog flag ADC2
+#define STM32F4_ADC_CSR_OVR1 BSP_BIT32(5) // Overrun flag ADC1
+#define STM32F4_ADC_CSR_STRT1 BSP_BIT32(4) // Regular start flag ADC1
+#define STM32F4_ADC_CSR_JSTRT1 BSP_BIT32(3) // Injected start flag ADC1
+#define STM32F4_ADC_CSR_JEOC1 BSP_BIT32(2) // Injected channel end of conversion flag ADC1
+#define STM32F4_ADC_CSR_EOC1 BSP_BIT32(1) // Channel end of conversion flag ADC1
+#define STM32F4_ADC_CSR_AWD1 BSP_BIT32(0) // Analog watchdog flag ADC1
+
+ uint32_t ccr; // 0x00: Common control register
+#define STM32F4_ADC_CCR_TSVREFE BSP_BIT32(23) // Temp sensor and Vrefint enable
+#define STM32F4_ADC_CCR_VBATE BSP_BIT32(22) // Vbat enable
+#define STM32F4_ADC_CCR_ADCPRE(val) BSP_FLD32(val, 16, 17) // ADC prescalar
+#define STM32F4_ADC_CCR_ADCPRE_GET(reg) BSP_FLD32GET(reg, 16, 17)
+#define STM32F4_ADC_CCR_ADCPRE_SET(reg, val) BSP_FLD32SET(reg, val, 16, 17)
+#define ADC_ADCPRE_PCLK2_2 0
+#define ADC_ADCPRE_PCLK2_4 1
+#define ADC_ADCPRE_PCLK2_6 2
+#define ADC_ADCPRE_PCLK2_8 3
+#define STM32F4_ADC_CCR_DMA(val) BSP_FLD32(val, 14, 15) // DMA access mode for multi ADC
+#define STM32F4_ADC_CCR_DMA_GET(reg) BSP_FLD32GET(reg, 14, 15)
+#define STM32F4_ADC_CCR_DMA_SET(reg, val) BSP_FLD32SET(reg, val, 14, 15)
+#define ADC_DMA_DISABLE 0
+#define ADC_DMA_MODE1 1
+#define ADC_DMA_MODE2 2
+#define ADC_DMA_MODE3 3
+#define STM32F4_ADC_CCR_DDS BSP_BIT32(13) // DMA disable selection
+#define STM32F4_ADC_CCR_DELAY(val) BSP_FLD32(val, 8, 11) // Delay between sampling phases
+#define STM32F4_ADC_CCR_DELAY_GET(reg) BSP_FLD32GET(reg, 8, 11)
+#define STM32F4_ADC_CCR_DELAY_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11)
+#define ADC_DELAY_5T 0
+#define ADC_DELAY_6T 1
+#define ADC_DELAY_7T 2
+#define ADC_DELAY_8T 3
+#define ADC_DELAY_9T 4
+#define ADC_DELAY_10T 5
+#define ADC_DELAY_11T 6
+#define ADC_DELAY_12T 7
+#define ADC_DELAY_13T 8
+#define ADC_DELAY_14T 9
+#define ADC_DELAY_15T 10
+#define ADC_DELAY_16T 11
+#define ADC_DELAY_17T 12
+#define ADC_DELAY_18T 13
+#define ADC_DELAY_19T 14
+#define ADC_DELAY_20T 15
+#define STM32F4_ADC_CCR_MULTI(val) BSP_FLD32(val, 0, 4) // Multi ADC mode
+#define STM32F4_ADC_CCR_MULTI_GET(reg) BSP_FLD32GET(reg, 0, 4)
+#define STM32F4_ADC_CCR_MULTI_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4)
+#define ADC_MULTI_INDEPENDENT 0x00
+#define ADC_MULTI_DUAL_REG_INJ 0x01
+#define ADC_MULTI_DUAL_REG_ALT 0x02
+#define ADC_MULTI_DUAL_INJ 0x05
+#define ADC_MULTI_DUAL_REG 0x06
+#define ADC_MULTI_DUAL_INTRL 0x07
+#define ADC_MULTI_DUAL_ALT_TRIG 0x09
+#define ADC_MULTI_TRIPLE_REG_INJ 0x11
+#define ADC_MULTI_TRIPLE_REG_ALT 0x12
+#define ADC_MULTI_TRIPLE_INJ 0x15
+#define ADC_MULTI_TRIPLE_REG 0x16
+#define ADC_MULTI_TRIPLE_INTRL 0x17
+#define ADC_MULTI_TRIPLE_ALT_TRIG 0x19
+
+ uint32_t cdr; // 0x00: Common regular data register
+#define STM32F4_ADC_CDR_DATA2(val) BSP_FLD32(val, 16, 31) // 2nd data item
+#define STM32F4_ADC_CDR_DATA2_GET(reg) BSP_FLD32GET(reg, 16, 31)
+#define STM32F4_ADC_CDR_DATA2_SET(reg, val) BSP_FLD32SET(reg, val, 16, 31)
+#define STM32F4_ADC_CDR_DATA1(val) BSP_FLD32(val, 0, 15) // 1st data item
+#define STM32F4_ADC_CDR_DATA1_GET(reg) BSP_FLD32GET(reg, 0, 15)
+#define STM32F4_ADC_CDR_DATA1_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15)
+
+} __attribute__ ((packed));
+typedef struct stm32f4_adc_com_s stm32f4_adc_com;
+
+#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_ADC_H */
diff --git a/c/src/lib/libbsp/arm/stm32f4/preinstall.am b/c/src/lib/libbsp/arm/stm32f4/preinstall.am
index 40fdc7f..d22b578 100644
--- a/c/src/lib/libbsp/arm/stm32f4/preinstall.am
+++ b/c/src/lib/libbsp/arm/stm32f4/preinstall.am
@@ -117,6 +117,10 @@ $(PROJECT_INCLUDE)/bsp/stm32f10xxx_exti.h: include/stm32f10xxx_exti.h $(PROJECT_
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f10xxx_exti.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f10xxx_exti.h
+$(PROJECT_INCLUDE)/bsp/stm32f4xxxx_adc.h: include/stm32f4xxxx_adc.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_adc.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_adc.h
+
$(PROJECT_INCLUDE)/bsp/stm32f4xxxx_exti.h: include/stm32f4xxxx_exti.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_exti.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stm32f4xxxx_exti.h
--
1.8.4.2
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