[PATCH 1/2] bsp/sparc: Flush icache before first time enabling interrupts

Sebastian Huber sebastian.huber at embedded-brains.de
Fri Jul 4 06:44:43 UTC 2014

On 2014-07-03 11:39, Daniel Cederman wrote:
> A secondary processor might miss changes done to the trap table
> if the instruction cache is not flushed. Once interrupts are enabled
> any other required cache flushes can be ordered via the cache
> manager.

I think it is a general bug if you change the trap responsible for the IPI 
after the start request of the secondary processors.  At which point does this 
problem happen currently?

Sebastian Huber, embedded brains GmbH

Address : Dornierstr. 4, D-82178 Puchheim, Germany
Phone   : +49 89 189 47 41-16
Fax     : +49 89 189 47 41-09
E-Mail  : sebastian.huber at embedded-brains.de
PGP     : Public key available on request.

Diese Nachricht ist keine geschäftliche Mitteilung im Sinne des EHUG.

More information about the devel mailing list