[PATCH 1/2] bsp/sparc: Flush icache before first time enabling interrupts

[Sebastian Huber]

On 2014-07-03 11:39, Daniel Cederman wrote:
> A secondary processor might miss changes done to the trap table
> if the instruction cache is not flushed. Once interrupts are enabled
> any other required cache flushes can be ordered via the cache
> manager.

I think it is a general bug if you change the trap responsible for the IPI 
after the start request of the secondary processors.  At which point does this 
problem happen currently?

-- 
Sebastian Huber, embedded brains GmbH

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