[PATCH 1/2] bsp/sparc: Flush icache before first time enabling interrupts

[Daniel Cederman]

 > I think it is a general bug if you change the trap responsible for the
 > IPI after the start request of the secondary processors.  At which point
 > does this problem happen currently?

The trap responsible for IPIs is only set before the secondary 
processors are started and is not changed after that, so that is no 
problem. But other traps are set after the secondary processors are 
started, but before we can send IPIs. These changes might be missed.

Daniel Cederman
Software Engineer
Aeroflex Gaisler AB
Aeroflex Microelectronic Solutions – HiRel
Kungsgatan 12
SE-411 19 Gothenburg, Sweden
Phone: +46 31 7758665
cederman at gaisler.com
www.Aeroflex.com/Gaisler

On 2014-07-04 08:44, Sebastian Huber wrote:
> On 2014-07-03 11:39, Daniel Cederman wrote:
>> A secondary processor might miss changes done to the trap table
>> if the instruction cache is not flushed. Once interrupts are enabled
>> any other required cache flushes can be ordered via the cache
>> manager.
>
> I think it is a general bug if you change the trap responsible for the
> IPI after the start request of the secondary processors.  At which point
> does this problem happen currently?
>