[PATCH-V2 7/7] bsp/sparc: Flush only instruction cache

[Daniel Cederman]

On 2014-07-09 16:40, Gedare Bloom wrote:
> On Wed, Jul 9, 2014 at 3:02 AM, Daniel Cederman <cederman at gaisler.com> wrote:
>> The flush instruction on LEON flushes both the data and the instruction
>> cache. Flushing of just the instruction cache can be done by setting
>> the "flush instruction cache" bit in the cache control register.
>> ---
>>   c/src/lib/libbsp/sparc/leon3/include/cache_.h |    5 ++++-
>>   c/src/lib/libbsp/sparc/leon3/include/leon.h   |    1 +
>>   2 files changed, 5 insertions(+), 1 deletion(-)
>>
>> diff --git a/c/src/lib/libbsp/sparc/leon3/include/cache_.h b/c/src/lib/libbsp/sparc/leon3/include/cache_.h
>> index 63790c1..ced5b6d 100644
>> --- a/c/src/lib/libbsp/sparc/leon3/include/cache_.h
>> +++ b/c/src/lib/libbsp/sparc/leon3/include/cache_.h
>> @@ -136,7 +136,10 @@ static inline void _CPU_cache_unfreeze_data(void)
>>
>>   static inline void _CPU_cache_invalidate_entire_instruction(void)
>>   {
>> -  __asm__ volatile ("flush");
>> +  uint32_t cache_reg = leon3_get_cache_control_register();
>> +
>> +  cache_reg |= LEON3_REG_CACHE_CTRL_FI;
>> +  leon3_set_cache_control_register(cache_reg);
>>   }
> Now you should also flush the d-cache explicitly for the case of
> updating the trap table, as I mentioned in my previous email the store
> to tbr[] can get cached in d-cache, so if we don't flush d-cache to
> memory and it is write-back cache, there could be a problem. (I don't
> know whether sparc32 cache are write-back or write-thru.)
>
> -Gedare
>

The cache is write-thru so there should not be any need to flush the 
d-cache.

>>
>>   static inline void _CPU_cache_invalidate_instruction_range(
>> diff --git a/c/src/lib/libbsp/sparc/leon3/include/leon.h b/c/src/lib/libbsp/sparc/leon3/include/leon.h
>> index a62ad29..bc3cdde 100644
>> --- a/c/src/lib/libbsp/sparc/leon3/include/leon.h
>> +++ b/c/src/lib/libbsp/sparc/leon3/include/leon.h
>> @@ -90,6 +90,7 @@ extern "C" {
>>    *  The following defines the bits in the LEON Cache Control Register.
>>    */
>>   #define LEON3_REG_CACHE_CTRL_DS      0x00800000 /* Data cache snooping */
>> +#define LEON3_REG_CACHE_CTRL_FI      0x00200000 /* Flush instruction cache */
>>
>>   /* LEON3 Interrupt Controller */
>>   extern volatile struct irqmp_regs *LEON3_IrqCtrl_Regs;
>> --
>> 1.7.9.5
>>
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