ERC32 with FPU rev.B or rev.C

[Sebastian Huber]

Hello,

there is a fix for the ERC32 with FPU rev.B or rev.C in the SPARC interrupt 
entry code:

http://git.rtems.org/rtems/tree/c/src/lib/libbsp/sparc/shared/irq_asm.S#n426

Exists there systems with such a processor?  Is it reasonable to ship RTEMS 
4.11 or later on such a system?

I would like to remove this code block.

-- 
Sebastian Huber, embedded brains GmbH

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