ERC32 with FPU rev.B or rev.C

[Jiri Gaisler]

These fixes are no longer necessary, the silicon has been fixed
long time ago. The only real use of these early chip revisions
were in the GNC computers of the Space Station (!), where they
run a modified version of VxWorks 5.1 ... :-)

Jiri.

On 03/05/2014 09:25 AM, Sebastian Huber wrote:
> Hello,
> 
> there is a fix for the ERC32 with FPU rev.B or rev.C in the SPARC interrupt entry code:
> 
> http://git.rtems.org/rtems/tree/c/src/lib/libbsp/sparc/shared/irq_asm.S#n426
> 
> Exists there systems with such a processor?  Is it reasonable to ship RTEMS 4.11 or later on such a system?
> 
> I would like to remove this code block.
>