[PATCH 1/2] libcpu/or1k: Fix warnings.

[Joel Sherrill]

On 10/13/2014 11:45 AM, Hesham Moustafa wrote:
> Missed patch?
>
Yep. Committed now. This should address a bunch of the or1ksim
build warnings. I fixed another in console/uart.c for an unused
variable.

Starting another build of all BSPs to see if I fixed all
"-Wunused-variables"
cases.

Thanks.
> On Fri, Oct 10, 2014 at 7:23 PM, Hesham ALMatary
> <heshamelmatary at gmail.com <mailto:heshamelmatary at gmail.com>> wrote:
>
>     ---
>      c/src/lib/libcpu/or1k/shared/cache/cache.c  | 16 ++++++++--------
>      c/src/lib/libcpu/or1k/shared/cache/cache_.h |  1 +
>      2 files changed, 9 insertions(+), 8 deletions(-)
>
>     diff --git a/c/src/lib/libcpu/or1k/shared/cache/cache.c
>     b/c/src/lib/libcpu/or1k/shared/cache/cache.c
>     index 039be36..afc8859 100644
>     --- a/c/src/lib/libcpu/or1k/shared/cache/cache.c
>     +++ b/c/src/lib/libcpu/or1k/shared/cache/cache.c
>     @@ -71,7 +71,7 @@ static inline void
>     _CPU_OR1K_Cache_data_block_prefetch(const void *d_addr)
>
>        _ISR_Disable (level);
>
>     -  _OR1K_mtspr(CPU_OR1K_SPR_DCBPR, d_addr);
>     +  _OR1K_mtspr(CPU_OR1K_SPR_DCBPR, (uintptr_t) d_addr);
>
>        _ISR_Enable(level);
>      }
>     @@ -81,7 +81,7 @@ static inline void
>     _CPU_OR1K_Cache_data_block_flush(const void *d_addr)
>         ISR_Level level;
>        _ISR_Disable (level);
>
>     -  _OR1K_mtspr(CPU_OR1K_SPR_DCBFR, d_addr);
>     +  _OR1K_mtspr(CPU_OR1K_SPR_DCBFR, (uintptr_t) d_addr);
>
>        _ISR_Enable(level);
>      }
>     @@ -91,7 +91,7 @@ static inline void
>     _CPU_OR1K_Cache_data_block_invalidate(const void *d_addr)
>         ISR_Level level;
>        _ISR_Disable (level);
>
>     -  _OR1K_mtspr(CPU_OR1K_SPR_DCBIR, d_addr);
>     +  _OR1K_mtspr(CPU_OR1K_SPR_DCBIR, (uintptr_t) d_addr);
>
>        _ISR_Enable(level);
>      }
>     @@ -101,7 +101,7 @@ static inline void
>     _CPU_OR1K_Cache_data_block_writeback(const void *d_addr)
>         ISR_Level level;
>        _ISR_Disable (level);
>
>     -  _OR1K_mtspr(CPU_OR1K_SPR_DCBWR, d_addr);
>     +  _OR1K_mtspr(CPU_OR1K_SPR_DCBWR, (uintptr_t) d_addr);
>
>        _ISR_Enable(level);
>      }
>     @@ -111,7 +111,7 @@ static inline void
>     _CPU_OR1K_Cache_data_block_lock(const void *d_addr)
>         ISR_Level level;
>        _ISR_Disable (level);
>
>     -  _OR1K_mtspr(CPU_OR1K_SPR_DCBLR, d_addr);
>     +  _OR1K_mtspr(CPU_OR1K_SPR_DCBLR, (uintptr_t) d_addr);
>
>        _ISR_Enable(level);
>      }
>     @@ -122,7 +122,7 @@ static inline void
>     _CPU_OR1K_Cache_instruction_block_prefetch
>         ISR_Level level;
>        _ISR_Disable (level);
>
>     -  _OR1K_mtspr(CPU_OR1K_SPR_ICBPR, d_addr);
>     +  _OR1K_mtspr(CPU_OR1K_SPR_ICBPR, (uintptr_t) d_addr);
>
>        _ISR_Enable(level);
>      }
>     @@ -133,7 +133,7 @@ static inline void
>     _CPU_OR1K_Cache_instruction_block_invalidate
>         ISR_Level level;
>        _ISR_Disable (level);
>
>     -  _OR1K_mtspr(CPU_OR1K_SPR_ICBIR, d_addr);
>     +  _OR1K_mtspr(CPU_OR1K_SPR_ICBIR, (uintptr_t) d_addr);
>
>        _ISR_Enable(level);
>      }
>     @@ -144,7 +144,7 @@ static inline void
>     _CPU_OR1K_Cache_instruction_block_lock
>         ISR_Level level;
>        _ISR_Disable (level);
>
>     -  _OR1K_mtspr(CPU_OR1K_SPR_ICBLR, d_addr);
>     +  _OR1K_mtspr(CPU_OR1K_SPR_ICBLR, (uintptr_t) d_addr);
>
>        _ISR_Enable(level);
>      }
>     diff --git a/c/src/lib/libcpu/or1k/shared/cache/cache_.h
>     b/c/src/lib/libcpu/or1k/shared/cache/cache_.h
>     index 5f08410..0ea939f 100644
>     --- a/c/src/lib/libcpu/or1k/shared/cache/cache_.h
>     +++ b/c/src/lib/libcpu/or1k/shared/cache/cache_.h
>     @@ -6,6 +6,7 @@
>      #define __OR1K_CACHE_H
>
>      #include <bsp/cache_.h>
>     +#include <libcpu/cache.h>
>
>      #endif
>      /* end of include file */
>     --
>     1.9.3
>
>

-- 
Joel Sherrill, Ph.D.             Director of Research & Development
joel.sherrill at OARcorp.com        On-Line Applications Research
Ask me about RTEMS: a free RTOS  Huntsville AL 35805
Support Available                (256) 722-9985

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