[PATCH] or1k: New cache manager.
Hesham Moustafa
heshamelmatary at gmail.com
Tue Sep 16 17:54:10 UTC 2014
Hi
On Tue, Sep 16, 2014 at 7:47 PM, Joel Sherrill
<joel.sherrill at oarcorp.com> wrote:
> I don't understand this but I got it applied.
>
> I manually edited the saved email to delete the preinstall.am
> changes. I committed the rest. Then I ran bootstrap -p myself
> and folded that into the rest of your patch.
>
> It should all be committed now.
>
Thanks for doing this, me too do not know what's wrong. BTW, commits
are not mirrored on github since 4 days ago.
> How about some new test results. :)
>
I did run one last night, no big progress since previous results :( Is
there any tool, script, utility program or whatever that I can use to
detect wrong memory access (i.e, stack overwrite, heap corruption,
access to another task context)? I tried to add -fstack-protector-all
to gcc, but QEMU did not get anything or core-dump, ticker just hangs.
> --joel
> On 9/16/2014 12:30 PM, Hesham ALMatary wrote:
>> Implement new cache functions for or1k and create new bspstart function
>> for or1ksim to initialize instruction and data caches. Also, sim.cfg
>> is modified to enable/confiure cache units.
>> ---
>> c/src/lib/libbsp/or1k/or1ksim/Makefile.am | 9 +-
>> c/src/lib/libbsp/or1k/or1ksim/preinstall.am | 4 +
>> c/src/lib/libbsp/or1k/or1ksim/sim.cfg | 21 +-
>> c/src/lib/libbsp/or1k/or1ksim/startup/bspstart.c | 25 +++
>> c/src/lib/libbsp/or1k/shared/include/cache_.h | 43 ++++
>> c/src/lib/libcpu/or1k/Makefile.am | 3 +-
>> c/src/lib/libcpu/or1k/preinstall.am | 4 +
>> c/src/lib/libcpu/or1k/shared/cache/cache.c | 241 +++++++++++++++++++++++
>> c/src/lib/libcpu/or1k/shared/cache/cache_.h | 2 +-
>> 9 files changed, 334 insertions(+), 18 deletions(-)
>> create mode 100644 c/src/lib/libbsp/or1k/or1ksim/startup/bspstart.c
>> create mode 100644 c/src/lib/libbsp/or1k/shared/include/cache_.h
>> create mode 100644 c/src/lib/libcpu/or1k/shared/cache/cache.c
>>
>> diff --git a/c/src/lib/libbsp/or1k/or1ksim/Makefile.am b/c/src/lib/libbsp/or1k/or1ksim/Makefile.am
>> index 7af4fd0..7e1c10b 100644
>> --- a/c/src/lib/libbsp/or1k/or1ksim/Makefile.am
>> +++ b/c/src/lib/libbsp/or1k/or1ksim/Makefile.am
>> @@ -30,6 +30,7 @@ include_bsp_HEADERS += ../../shared/include/irq-info.h
>> include_bsp_HEADERS += ../../shared/include/stackalloc.h
>> include_bsp_HEADERS += ../../shared/include/uart-output-char.h
>> include_bsp_HEADERS += ../../shared/tod.h
>> +include_bsp_HEADERS += ../shared/include/cache_.h
>> include_bsp_HEADERS += include/irq.h
>> include_bsp_HEADERS += include/uart.h
>> include_bsp_HEADERS += include/or1ksim.h
>> @@ -61,8 +62,8 @@ libbsp_a_CPPFLAGS =
>> libbsp_a_LIBADD =
>>
>> # Startup
>> -libbsp_a_SOURCES += ../../shared/bspstart.c
>> libbsp_a_SOURCES += ../../shared/bspreset.c
>> +libbsp_a_SOURCES += startup/bspstart.c
>>
>> # Shared
>> libbsp_a_SOURCES += ../../shared/bootcard.c
>> @@ -72,8 +73,6 @@ libbsp_a_SOURCES += ../../shared/bsplibc.c
>> libbsp_a_SOURCES += ../../shared/bsppost.c
>> libbsp_a_SOURCES += ../../shared/bsppredriverhook.c
>> libbsp_a_SOURCES += ../../shared/bsppretaskinghook.c
>> -libbsp_a_SOURCES += ../../shared/cpucounterread.c
>> -libbsp_a_SOURCES += ../../shared/cpucounterdiff.c
>> libbsp_a_SOURCES += ../../shared/gnatinstallhandler.c
>> libbsp_a_SOURCES += ../../shared/sbrk.c
>> libbsp_a_SOURCES += ../../shared/src/stackalloc.c
>> @@ -100,9 +99,7 @@ libbsp_a_SOURCES += ../../shared/src/irq-info.c
>> libbsp_a_SOURCES += irq/irq.c
>>
>> # Cache
>> -libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c
>> -libbsp_a_SOURCES += ../../shared/include/cache_.h
>> -libbsp_a_CPPFLAGS += -I$(srcdir)/../../shared/include
>> +libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/shared/cache.rel
>>
>> ###############################################################################
>> # Special Rules #
>> diff --git a/c/src/lib/libbsp/or1k/or1ksim/preinstall.am b/c/src/lib/libbsp/or1k/or1ksim/preinstall.am
>> index 1561b18..c0fa6b8 100644
>> --- a/c/src/lib/libbsp/or1k/or1ksim/preinstall.am
>> +++ b/c/src/lib/libbsp/or1k/or1ksim/preinstall.am
>> @@ -86,6 +86,10 @@ $(PROJECT_INCLUDE)/bsp/tod.h: ../../shared/tod.h $(PROJECT_INCLUDE)/bsp/$(dirsta
>> $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tod.h
>> PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/tod.h
>>
>> +$(PROJECT_INCLUDE)/bsp/cache_.h: ../shared/include/cache_.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
>> + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/cache_.h
>> +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/cache_.h
>> +
>> $(PROJECT_INCLUDE)/bsp/irq.h: include/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
>> $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h
>> PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq.h
>> diff --git a/c/src/lib/libbsp/or1k/or1ksim/sim.cfg b/c/src/lib/libbsp/or1k/or1ksim/sim.cfg
>> index 061f61a..ec73e3d 100644
>> --- a/c/src/lib/libbsp/or1k/or1ksim/sim.cfg
>> +++ b/c/src/lib/libbsp/or1k/or1ksim/sim.cfg
>> @@ -35,23 +35,23 @@ section mc
>> end
>>
>> section ic
>> - enabled = 0
>> + enabled = 1
>> nsets = 256
>> nways = 1
>> - blocksize = 16
>> + blocksize = 32
>> hitdelay = 20
>> - missdelay = 20
>> + missdelay = 60
>> end
>>
>> section dc
>> - enabled = 0
>> - nsets = 256
>> + enabled = 1
>> + nsets = 256
>> nways = 1
>> - blocksize = 16
>> - load_hitdelay = 0
>> - load_missdelay = 0
>> - store_hitdelay = 0
>> - store_missdelay = 0
>> + blocksize = 32
>> + load_hitdelay = 40
>> + load_missdelay = 120
>> + store_hitdelay = 40
>> + store_missdelay = 120
>> end
>>
>> section pic
>> @@ -78,6 +78,7 @@ section cpu
>> ver = 0x12
>> cfg = 0x00
>> rev = 0x0001
>> + upr = 0x0000075f
>> superscalar = 0
>> hazards = 0
>> dependstats = 0
>> diff --git a/c/src/lib/libbsp/or1k/or1ksim/startup/bspstart.c b/c/src/lib/libbsp/or1k/or1ksim/startup/bspstart.c
>> new file mode 100644
>> index 0000000..d9fb7a7
>> --- /dev/null
>> +++ b/c/src/lib/libbsp/or1k/or1ksim/startup/bspstart.c
>> @@ -0,0 +1,25 @@
>> +/**
>> + * @file
>> + *
>> + * @ingroup or1ksim
>> + *
>> + * @brief Benchmark timer support.
>> + */
>> +
>> +/*
>> + * Copyright (c) 2014 by Hesham ALMatary
>> + *
>> + * The license and distribution terms for this file may be
>> + * found in the file LICENSE in this distribution or at
>> + * http://www.rtems.org/license/LICENSE
>> + */
>> +
>> +#include <bsp.h>
>> +#include <bsp/bootcard.h>
>> +#include <libcpu/cache.h>
>> +
>> +void bsp_start( void )
>> +{
>> + _CPU_cache_enable_instruction();
>> + _CPU_cache_enable_data();
>> +}
>> diff --git a/c/src/lib/libbsp/or1k/shared/include/cache_.h b/c/src/lib/libbsp/or1k/shared/include/cache_.h
>> new file mode 100644
>> index 0000000..ee54227
>> --- /dev/null
>> +++ b/c/src/lib/libbsp/or1k/shared/include/cache_.h
>> @@ -0,0 +1,43 @@
>> +/*
>> + * COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary at gmail.com>
>> + *
>> + * The license and distribution terms for this file may be
>> + * found in the file LICENSE in this distribution or at
>> + * http://www.rtems.org/license/LICENSE.
>> + */
>> +
>> +#ifndef LIBBSP_OR1K_SHARED_CACHE_H
>> +#define LIBBSP_OR1K_SHARED_CACHE_H
>> +
>> +#include <assert.h>
>> +#include <bsp.h>
>> +#include <rtems/rtems/intr.h>
>> +
>> +
>> +#ifdef __cplusplus
>> +extern "C" {
>> +#endif /* __cplusplus */
>> +
>> +/* These two defines also ensure that the rtems_cache_* functions have bodies */
>> +#define CPU_DATA_CACHE_ALIGNMENT 32
>> +#define CPU_INSTRUCTION_CACHE_ALIGNMENT 32
>> +
>> +#define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS 1
>> +
>> +static inline size_t
>> +_CPU_cache_get_data_cache_size( const uint32_t level )
>> +{
>> + return (level == 0 || level == 1)? 8192 : 0;
>> +}
>> +
>> +static inline size_t
>> +_CPU_cache_get_instruction_cache_size( const uint32_t level )
>> +{
>> + return (level == 0 || level == 1)? 8192 : 0;
>> +}
>> +
>> +#ifdef __cplusplus
>> +}
>> +#endif /* __cplusplus */
>> +
>> +#endif /* LIBBSP_OR1K_SHARED_CACHE_H */
>> diff --git a/c/src/lib/libcpu/or1k/Makefile.am b/c/src/lib/libcpu/or1k/Makefile.am
>> index f4a6372..0148548 100644
>> --- a/c/src/lib/libcpu/or1k/Makefile.am
>> +++ b/c/src/lib/libcpu/or1k/Makefile.am
>> @@ -10,8 +10,9 @@ include_libcpudir = $(includedir)/libcpu
>>
>> ## shared/cache
>> include_libcpu_HEADERS = ../shared/include/cache.h
>> +include_libcpu_HEADERS += shared/cache/cache_.h
>> noinst_PROGRAMS += shared/cache.rel
>> -shared_cache_rel_SOURCES = ../shared/src/no_cache.c shared/cache/cache_.h
>> +shared_cache_rel_SOURCES = shared/cache/cache.c ../shared/src/cache_manager.c
>> shared_cache_rel_CPPFLAGS = $(AM_CPPFLAGS) -I$(srcdir)/shared/cache
>> shared_cache_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
>>
>> diff --git a/c/src/lib/libcpu/or1k/preinstall.am b/c/src/lib/libcpu/or1k/preinstall.am
>> index ee9d0da..84864cb 100644
>> --- a/c/src/lib/libcpu/or1k/preinstall.am
>> +++ b/c/src/lib/libcpu/or1k/preinstall.am
>> @@ -22,3 +22,7 @@ $(PROJECT_INCLUDE)/libcpu/cache.h: ../shared/include/cache.h $(PROJECT_INCLUDE)/
>> $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/cache.h
>> PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/cache.h
>>
>> +$(PROJECT_INCLUDE)/libcpu/cache_.h: shared/cache/cache_.h $(PROJECT_INCLUDE)/libcpu/$(dirstamp)
>> + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/libcpu/cache_.h
>> +PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu/cache_.h
>> +
>> diff --git a/c/src/lib/libcpu/or1k/shared/cache/cache.c b/c/src/lib/libcpu/or1k/shared/cache/cache.c
>> new file mode 100644
>> index 0000000..fdc67ce
>> --- /dev/null
>> +++ b/c/src/lib/libcpu/or1k/shared/cache/cache.c
>> @@ -0,0 +1,241 @@
>> +/*
>> + * COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary at gmail.com>
>> + *
>> + * COPYRIGHT (c) 1989-2006
>> + * On-Line Applications Research Corporation (OAR).
>> + *
>> + * The license and distribution terms for this file may be
>> + * found in the file LICENSE in this distribution or at
>> + * http://www.rtems.org/license/LICENSE.
>> + */
>> +
>> +#include <rtems/score/cpu.h>
>> +#include <rtems/score/interr.h>
>> +#include <rtems/score/or1k-utility.h>
>> +#include <libcpu/cache.h>
>> +
>> +static inline void _CPU_OR1K_Cache_enable_data(void)
>> +{
>> + uint32_t sr;
>> + ISR_Level level;
>> +
>> + _ISR_Disable (level);
>> + sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
>> + _OR1K_mtspr(CPU_OR1K_SPR_SR, sr | CPU_OR1K_SPR_SR_DCE);
>> +
>> + _ISR_Enable(level);
>> +}
>> +
>> +static inline void _CPU_OR1K_Cache_disable_data(void)
>> +{
>> + uint32_t sr;
>> + ISR_Level level;
>> +
>> + _ISR_Disable (level);
>> +
>> + sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
>> + _OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~CPU_OR1K_SPR_SR_DCE));
>> +
>> + _ISR_Enable(level);
>> +}
>> +
>> +static inline void _CPU_OR1K_Cache_enable_instruction(void)
>> +{
>> + uint32_t sr;
>> + ISR_Level level;
>> +
>> + _ISR_Disable (level);
>> +
>> + sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
>> + _OR1K_mtspr(CPU_OR1K_SPR_SR, sr | CPU_OR1K_SPR_SR_ICE);
>> +
>> + _ISR_Enable(level);
>> +}
>> +
>> +static inline void _CPU_OR1K_Cache_disable_instruction(void)
>> +{
>> + uint32_t sr;
>> + ISR_Level level;
>> +
>> + _ISR_Disable (level);
>> +
>> + sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
>> + _OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~CPU_OR1K_SPR_SR_ICE));
>> +
>> + _ISR_Enable(level);
>> +}
>> +
>> +static inline void _CPU_OR1K_Cache_data_block_prefetch(const void *d_addr)
>> +{
>> + ISR_Level level;
>> +
>> + _ISR_Disable (level);
>> +
>> + _OR1K_mtspr(CPU_OR1K_SPR_DCBPR, d_addr);
>> +
>> + _ISR_Enable(level);
>> +}
>> +
>> +static inline void _CPU_OR1K_Cache_data_block_flush(const void *d_addr)
>> +{
>> + ISR_Level level;
>> + _ISR_Disable (level);
>> +
>> + _OR1K_mtspr(CPU_OR1K_SPR_DCBFR, d_addr);
>> +
>> + _ISR_Enable(level);
>> +}
>> +
>> +static inline void _CPU_OR1K_Cache_data_block_invalidate(const void *d_addr)
>> +{
>> + ISR_Level level;
>> + _ISR_Disable (level);
>> +
>> + _OR1K_mtspr(CPU_OR1K_SPR_DCBIR, d_addr);
>> +
>> + _ISR_Enable(level);
>> +}
>> +
>> +static inline void _CPU_OR1K_Cache_data_block_writeback(const void *d_addr)
>> +{
>> + ISR_Level level;
>> + _ISR_Disable (level);
>> +
>> + _OR1K_mtspr(CPU_OR1K_SPR_DCBWR, d_addr);
>> +
>> + _ISR_Enable(level);
>> +}
>> +
>> +static inline void _CPU_OR1K_Cache_data_block_lock(const void *d_addr)
>> +{
>> + ISR_Level level;
>> + _ISR_Disable (level);
>> +
>> + _OR1K_mtspr(CPU_OR1K_SPR_DCBLR, d_addr);
>> +
>> + _ISR_Enable(level);
>> +}
>> +
>> +static inline void _CPU_OR1K_Cache_instruction_block_prefetch
>> +(const void *d_addr)
>> +{
>> + ISR_Level level;
>> + _ISR_Disable (level);
>> +
>> + _OR1K_mtspr(CPU_OR1K_SPR_ICBPR, d_addr);
>> +
>> + _ISR_Enable(level);
>> +}
>> +
>> +static inline void _CPU_OR1K_Cache_instruction_block_invalidate
>> +(const void *d_addr)
>> +{
>> + ISR_Level level;
>> + _ISR_Disable (level);
>> +
>> + _OR1K_mtspr(CPU_OR1K_SPR_ICBIR, d_addr);
>> +
>> + _ISR_Enable(level);
>> +}
>> +
>> +static inline void _CPU_OR1K_Cache_instruction_block_lock
>> +(const void *d_addr)
>> +{
>> + ISR_Level level;
>> + _ISR_Disable (level);
>> +
>> + _OR1K_mtspr(CPU_OR1K_SPR_ICBLR, d_addr);
>> +
>> + _ISR_Enable(level);
>> +}
>> +
>> +/* Implement RTEMS cache manager functions */
>> +
>> +void _CPU_cache_flush_1_data_line(const void *d_addr)
>> +{
>> + ISR_Level level;
>> + _ISR_Disable (level);
>> +
>> + _CPU_OR1K_Cache_data_block_flush(d_addr);
>> +
>> + //asm volatile("l.csync");
>> +
>> + _ISR_Enable(level);
>> +}
>> +
>> +void _CPU_cache_invalidate_1_data_line(const void *d_addr)
>> +{
>> + ISR_Level level;
>> + _ISR_Disable (level);
>> +
>> + _CPU_OR1K_Cache_data_block_invalidate(d_addr);
>> +
>> + _ISR_Enable(level);
>> +}
>> +
>> +void _CPU_cache_freeze_data(void)
>> +{
>> + /* Do nothing */
>> +}
>> +
>> +void _CPU_cache_unfreeze_data(void)
>> +{
>> + /* Do nothing */
>> +}
>> +
>> +void _CPU_cache_invalidate_1_instruction_line(const void *d_addr)
>> +{
>> + ISR_Level level;
>> + _ISR_Disable (level);
>> +
>> + _CPU_OR1K_Cache_instruction_block_invalidate(d_addr);
>> +
>> + _ISR_Enable(level);
>> +}
>> +
>> +void _CPU_cache_freeze_instruction(void)
>> +{
>> + /* Do nothing */
>> +}
>> +
>> +void _CPU_cache_unfreeze_instruction(void)
>> +{
>> + /* Do nothing */
>> +}
>> +
>> +void _CPU_cache_flush_entire_data(void)
>> +{
>> +
>> +}
>> +
>> +void _CPU_cache_invalidate_entire_data(void)
>> +{
>> +
>> +}
>> +
>> +void _CPU_cache_invalidate_entire_instruction(void)
>> +{
>> +
>> +}
>> +
>> +void _CPU_cache_enable_data(void)
>> +{
>> + _CPU_OR1K_Cache_enable_data();
>> +}
>> +
>> +void _CPU_cache_disable_data(void)
>> +{
>> + _CPU_OR1K_Cache_disable_data();
>> +
>> +}
>> +
>> +void _CPU_cache_enable_instruction(void)
>> +{
>> +
>> + _CPU_OR1K_Cache_enable_instruction();
>> +}
>> +
>> +void _CPU_cache_disable_instruction(void)
>> +{
>> + _CPU_OR1K_Cache_disable_instruction();
>> +}
>> diff --git a/c/src/lib/libcpu/or1k/shared/cache/cache_.h b/c/src/lib/libcpu/or1k/shared/cache/cache_.h
>> index 08d9ecc..5f08410 100644
>> --- a/c/src/lib/libcpu/or1k/shared/cache/cache_.h
>> +++ b/c/src/lib/libcpu/or1k/shared/cache/cache_.h
>> @@ -5,7 +5,7 @@
>> #ifndef __OR1K_CACHE_H
>> #define __OR1K_CACHE_H
>>
>> -#include <libcpu/cache.h>
>> +#include <bsp/cache_.h>
>>
>> #endif
>> /* end of include file */
>> --
>> 1.9.3
>>
>> _______________________________________________
>> devel mailing list
>> devel at rtems.org
>> http://lists.rtems.org/mailman/listinfo/devel
>
> --
> Joel Sherrill, Ph.D. Director of Research & Development
> joel.sherrill at OARcorp.com On-Line Applications Research
> Ask me about RTEMS: a free RTOS Huntsville AL 35805
> Support Available (256) 722-9985
>
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