[PATCH 020/111] LEON: updated and added PCI peripherals for LEON BSPs
Daniel Hellstrom
daniel at gaisler.com
Thu Feb 26 16:38:22 UTC 2015
The CCHIP driver is replaced with the GR_701 driver. The
RASTA driver is replaced by the GR-RASTA-IO driver.
All drivers are now compatible with both LEON2 and LEON3,
drivers were initialized directly by the PCI-board drivers
are now initialized by the driver manager and therefore
does not require the double code created by including for
example grcan.c into grcan_rasta.c. The other drivers needs
to be updated to the driver manager framework however.
Added support for:
* GR-701 (only LEON2 before)
* GR-RASTA-IO (only LEON2 before)
* GR-RASTA-ADCDAC
* GR-RASTA-TMTC
* GR-RASTA-SPW-ROUTER
* GR-TMTC-1553
---
c/src/lib/libbsp/sparc/Makefile.am | 29 +-
c/src/lib/libbsp/sparc/leon2/Makefile.am | 55 +-
c/src/lib/libbsp/sparc/leon2/cchip/cchip.c | 375 -----------
c/src/lib/libbsp/sparc/leon2/include/cchip.h | 42 --
c/src/lib/libbsp/sparc/leon2/include/rasta.h | 132 ----
c/src/lib/libbsp/sparc/leon2/preinstall.am | 100 ++--
c/src/lib/libbsp/sparc/leon2/rasta/rasta.c | 386 -----------
c/src/lib/libbsp/sparc/leon3/Makefile.am | 31 +-
c/src/lib/libbsp/sparc/leon3/preinstall.am | 36 +-
c/src/lib/libbsp/sparc/shared/1553/b1553brm_pci.c | 135 ----
.../lib/libbsp/sparc/shared/1553/b1553brm_rasta.c | 117 ----
c/src/lib/libbsp/sparc/shared/can/grcan_rasta.c | 100 ---
c/src/lib/libbsp/sparc/shared/can/occan_pci.c | 65 --
.../lib/libbsp/sparc/shared/include/apbuart_pci.h | 47 --
.../libbsp/sparc/shared/include/apbuart_rasta.h | 47 --
.../lib/libbsp/sparc/shared/include/b1553brm_pci.h | 61 --
.../libbsp/sparc/shared/include/b1553brm_rasta.h | 61 --
c/src/lib/libbsp/sparc/shared/include/gr_701.h | 48 ++
.../libbsp/sparc/shared/include/gr_rasta_adcdac.h | 49 ++
.../lib/libbsp/sparc/shared/include/gr_rasta_io.h | 49 ++
.../libbsp/sparc/shared/include/gr_rasta_tmtc.h | 99 +++
.../lib/libbsp/sparc/shared/include/gr_tmtc_1553.h | 49 ++
.../lib/libbsp/sparc/shared/include/grcan_rasta.h | 29 -
c/src/lib/libbsp/sparc/shared/include/grspw_pci.h | 53 --
.../lib/libbsp/sparc/shared/include/grspw_rasta.h | 53 --
c/src/lib/libbsp/sparc/shared/include/occan_pci.h | 46 --
c/src/lib/libbsp/sparc/shared/pci/gr_701.c | 592 +++++++++++++++++
.../lib/libbsp/sparc/shared/pci/gr_rasta_adcdac.c | 661 +++++++++++++++++++
c/src/lib/libbsp/sparc/shared/pci/gr_rasta_io.c | 678 +++++++++++++++++++
.../libbsp/sparc/shared/pci/gr_rasta_spw_router.c | 675 +++++++++++++++++++
c/src/lib/libbsp/sparc/shared/pci/gr_rasta_tmtc.c | 684 ++++++++++++++++++++
c/src/lib/libbsp/sparc/shared/pci/gr_tmtc_1553.c | 571 ++++++++++++++++
c/src/lib/libbsp/sparc/shared/spw/grspw_pci.c | 132 ----
c/src/lib/libbsp/sparc/shared/spw/grspw_rasta.c | 158 -----
c/src/lib/libbsp/sparc/shared/uart/apbuart_pci.c | 44 --
c/src/lib/libbsp/sparc/shared/uart/apbuart_rasta.c | 43 --
36 files changed, 4272 insertions(+), 2260 deletions(-)
delete mode 100644 c/src/lib/libbsp/sparc/leon2/cchip/cchip.c
delete mode 100644 c/src/lib/libbsp/sparc/leon2/include/cchip.h
delete mode 100644 c/src/lib/libbsp/sparc/leon2/include/rasta.h
delete mode 100644 c/src/lib/libbsp/sparc/leon2/rasta/rasta.c
delete mode 100644 c/src/lib/libbsp/sparc/shared/1553/b1553brm_pci.c
delete mode 100644 c/src/lib/libbsp/sparc/shared/1553/b1553brm_rasta.c
delete mode 100644 c/src/lib/libbsp/sparc/shared/can/grcan_rasta.c
delete mode 100644 c/src/lib/libbsp/sparc/shared/can/occan_pci.c
delete mode 100644 c/src/lib/libbsp/sparc/shared/include/apbuart_pci.h
delete mode 100644 c/src/lib/libbsp/sparc/shared/include/apbuart_rasta.h
delete mode 100644 c/src/lib/libbsp/sparc/shared/include/b1553brm_pci.h
delete mode 100644 c/src/lib/libbsp/sparc/shared/include/b1553brm_rasta.h
create mode 100644 c/src/lib/libbsp/sparc/shared/include/gr_701.h
create mode 100644 c/src/lib/libbsp/sparc/shared/include/gr_rasta_adcdac.h
create mode 100644 c/src/lib/libbsp/sparc/shared/include/gr_rasta_io.h
create mode 100644 c/src/lib/libbsp/sparc/shared/include/gr_rasta_tmtc.h
create mode 100644 c/src/lib/libbsp/sparc/shared/include/gr_tmtc_1553.h
delete mode 100644 c/src/lib/libbsp/sparc/shared/include/grcan_rasta.h
delete mode 100644 c/src/lib/libbsp/sparc/shared/include/grspw_pci.h
delete mode 100644 c/src/lib/libbsp/sparc/shared/include/grspw_rasta.h
delete mode 100644 c/src/lib/libbsp/sparc/shared/include/occan_pci.h
create mode 100644 c/src/lib/libbsp/sparc/shared/pci/gr_701.c
create mode 100644 c/src/lib/libbsp/sparc/shared/pci/gr_rasta_adcdac.c
create mode 100644 c/src/lib/libbsp/sparc/shared/pci/gr_rasta_io.c
create mode 100644 c/src/lib/libbsp/sparc/shared/pci/gr_rasta_spw_router.c
create mode 100644 c/src/lib/libbsp/sparc/shared/pci/gr_rasta_tmtc.c
create mode 100644 c/src/lib/libbsp/sparc/shared/pci/gr_tmtc_1553.c
delete mode 100644 c/src/lib/libbsp/sparc/shared/spw/grspw_pci.c
delete mode 100644 c/src/lib/libbsp/sparc/shared/spw/grspw_rasta.c
delete mode 100644 c/src/lib/libbsp/sparc/shared/uart/apbuart_pci.c
delete mode 100644 c/src/lib/libbsp/sparc/shared/uart/apbuart_rasta.c
diff --git a/c/src/lib/libbsp/sparc/Makefile.am b/c/src/lib/libbsp/sparc/Makefile.am
index 3f0854e..719feba 100644
--- a/c/src/lib/libbsp/sparc/Makefile.am
+++ b/c/src/lib/libbsp/sparc/Makefile.am
@@ -42,45 +42,42 @@ EXTRA_DIST += shared/pci/pcif.c
EXTRA_DIST += shared/pci/pci_memreg_sparc_le.c
EXTRA_DIST += shared/pci/pci_memreg_sparc_be.c
+# PCI target boards
+EXTRA_DIST += shared/include/gr_701.h
+EXTRA_DIST += shared/include/gr_rasta_adcdac.h
+EXTRA_DIST += shared/include/gr_rasta_io.h
+EXTRA_DIST += shared/include/gr_rasta_tmtc.h
+EXTRA_DIST += shared/include/gr_tmtc_1553.h
+EXTRA_DIST += shared/pci/gr_701.c
+EXTRA_DIST += shared/pci/gr_rasta_adcdac.c
+EXTRA_DIST += shared/pci/gr_rasta_io.c
+EXTRA_DIST += shared/pci/gr_rasta_spw_router.c
+EXTRA_DIST += shared/pci/gr_rasta_tmtc.c
+EXTRA_DIST += shared/pci/gr_tmtc_1553.c
+
# DEBUG
EXTRA_DIST += shared/include/debug_defs.h
# SpaceWire (GRSPW)
EXTRA_DIST += shared/spw/grspw.c
-EXTRA_DIST += shared/spw/grspw_pci.c
-EXTRA_DIST += shared/spw/grspw_rasta.c
EXTRA_DIST += shared/include/grspw.h
-EXTRA_DIST += shared/include/grspw_pci.h
-EXTRA_DIST += shared/include/grspw_rasta.h
# UART
EXTRA_DIST += shared/uart/cons.c
EXTRA_DIST += shared/uart/apbuart_cons.c
EXTRA_DIST += shared/include/cons.h
EXTRA_DIST += shared/uart/apbuart.c
-EXTRA_DIST += shared/uart/apbuart_pci.c
-EXTRA_DIST += shared/uart/apbuart_rasta.c
EXTRA_DIST += shared/include/apbuart.h
-EXTRA_DIST += shared/include/apbuart_pci.h
-EXTRA_DIST += shared/include/apbuart_rasta.h
# CAN (OC_CAN, GRCAN)
EXTRA_DIST += shared/can/occan.c
-EXTRA_DIST += shared/can/occan_pci.c
EXTRA_DIST += shared/can/grcan.c
-EXTRA_DIST += shared/can/grcan_rasta.c
EXTRA_DIST += shared/include/occan.h
-EXTRA_DIST += shared/include/occan_pci.h
EXTRA_DIST += shared/include/grcan.h
-EXTRA_DIST += shared/include/grcan_rasta.h
# MIL-STD-B1553 (Core1553BRM)
EXTRA_DIST += shared/1553/b1553brm.c
-EXTRA_DIST += shared/1553/b1553brm_pci.c
-EXTRA_DIST += shared/1553/b1553brm_rasta.c
EXTRA_DIST += shared/include/b1553brm.h
-EXTRA_DIST += shared/include/b1553brm_pci.h
-EXTRA_DIST += shared/include/b1553brm_rasta.h
# I2C-master (I2CMST)
EXTRA_DIST += shared/i2c/i2cmst.c
diff --git a/c/src/lib/libbsp/sparc/leon2/Makefile.am b/c/src/lib/libbsp/sparc/leon2/Makefile.am
index e923025..008e203 100644
--- a/c/src/lib/libbsp/sparc/leon2/Makefile.am
+++ b/c/src/lib/libbsp/sparc/leon2/Makefile.am
@@ -8,21 +8,6 @@ dist_project_lib_DATA = bsp_specs
include_HEADERS = include/bsp.h
include_HEADERS += include/tm27.h
-include_HEADERS += include/rasta.h
-include_HEADERS += include/cchip.h
-include_HEADERS += ../../sparc/shared/include/grspw.h
-include_HEADERS += ../../sparc/shared/include/grspw_pci.h
-include_HEADERS += ../../sparc/shared/include/grspw_rasta.h
-include_HEADERS += ../../sparc/shared/include/occan.h
-include_HEADERS += ../../sparc/shared/include/occan_pci.h
-include_HEADERS += ../../sparc/shared/include/grcan.h
-include_HEADERS += ../../sparc/shared/include/grcan_rasta.h
-include_HEADERS += ../../sparc/shared/include/apbuart.h
-include_HEADERS += ../../sparc/shared/include/apbuart_pci.h
-include_HEADERS += ../../sparc/shared/include/apbuart_rasta.h
-include_HEADERS += ../../sparc/shared/include/b1553brm.h
-include_HEADERS += ../../sparc/shared/include/b1553brm_pci.h
-include_HEADERS += ../../sparc/shared/include/b1553brm_rasta.h
include_HEADERS += ../../sparc/shared/include/debug_defs.h
nodist_include_HEADERS = include/bspopts.h
@@ -111,30 +96,40 @@ libbsp_a_SOURCES += ../../sparc/shared/timer/tlib.c
include_HEADERS += ../../sparc/shared/include/grpci2.h
libbsp_a_SOURCES += ../../sparc/shared/pci/grpci2.c
libbsp_a_SOURCES += ../../sparc/shared/pci/grpci.c
+libbsp_a_SOURCES += ../../sparc/shared/pci/pcif.c
libbsp_a_SOURCES += ../../sparc/shared/pci/pci_memreg_sparc_le.c
libbsp_a_SOURCES += ../../sparc/shared/pci/pci_memreg_sparc_be.c
libbsp_a_SOURCES += pci/at697_pci.c
-# RASTA Kit
-libbsp_a_SOURCES += rasta/rasta.c
-# Companion Chip Kit
-libbsp_a_SOURCES += cchip/cchip.c
+# PCI target devices
+include_HEADERS += ../../sparc/shared/include/gr_701.h
+include_HEADERS += ../../sparc/shared/include/gr_rasta_adcdac.h
+include_HEADERS += ../../sparc/shared/include/gr_rasta_io.h
+include_HEADERS += ../../sparc/shared/include/gr_rasta_tmtc.h
+libbsp_a_SOURCES += ../../sparc/shared/pci/gr_701.c
+libbsp_a_SOURCES += ../../sparc/shared/pci/gr_rasta_adcdac.c
+libbsp_a_SOURCES += ../../sparc/shared/pci/gr_rasta_io.c
+libbsp_a_SOURCES += ../../sparc/shared/pci/gr_rasta_spw_router.c
+libbsp_a_SOURCES += ../../sparc/shared/pci/gr_rasta_tmtc.c
+
# B1553BRM
-libbsp_a_SOURCES += ../../sparc/shared/1553/b1553brm.c \
- ../../sparc/shared/1553/b1553brm_pci.c \
- ../../sparc/shared/1553/b1553brm_rasta.c
+include_HEADERS += ../../sparc/shared/include/b1553brm.h
+libbsp_a_SOURCES += ../../sparc/shared/1553/b1553brm.c
+
# CAN
+include_HEADERS += ../../sparc/shared/include/occan.h
+include_HEADERS += ../../sparc/shared/include/grcan.h
libbsp_a_SOURCES += ../../sparc/shared/can/occan.c \
- ../../sparc/shared/can/occan_pci.c \
- ../../sparc/shared/can/grcan.c \
- ../../sparc/shared/can/grcan_rasta.c
+ ../../sparc/shared/can/grcan.c
+
# SpaceWire
-libbsp_a_SOURCES += ../../sparc/shared/spw/grspw.c \
- ../../sparc/shared/spw/grspw_pci.c ../../sparc/shared/spw/grspw_rasta.c
+include_HEADERS += ../../sparc/shared/include/grspw.h
+libbsp_a_SOURCES += ../../sparc/shared/spw/grspw.c
+
# UART (RAW)
-libbsp_a_SOURCES += ../../sparc/shared/uart/apbuart.c \
- ../../sparc/shared/uart/apbuart_pci.c \
- ../../sparc/shared/uart/apbuart_rasta.c
+include_HEADERS += ../../sparc/shared/include/apbuart.h
+libbsp_a_SOURCES += ../../sparc/shared/uart/apbuart.c
+
# I2CMST
include_HEADERS += ../../sparc/shared/include/i2cmst.h
libbsp_a_SOURCES += ../../sparc/shared/i2c/i2cmst.c
diff --git a/c/src/lib/libbsp/sparc/leon2/cchip/cchip.c b/c/src/lib/libbsp/sparc/leon2/cchip/cchip.c
deleted file mode 100644
index 72419d5..0000000
--- a/c/src/lib/libbsp/sparc/leon2/cchip/cchip.c
+++ /dev/null
@@ -1,375 +0,0 @@
-/**
- * @file
- *
- * @ingroup cchip
- *
- * @brief GR-701 (Companion Chip) PCI board driver
- */
-
-/*
- * COPYRIGHT (c) 2007.
- * Aeroflex Gaisler AB.
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#include <bsp.h>
-#include <rtems/bspIo.h>
-#include <rtems.h>
-#include <string.h>
-
-#include <rtems.h>
-#include <leon.h>
-#include <ambapp.h>
-#include <pci.h>
-
-#include <b1553brm_pci.h>
-#include <occan_pci.h>
-#include <grspw_pci.h>
-#include <apbuart_pci.h>
-
-#include <cchip.h>
-
-/*
-#define DEBUG
-#define DEBUG_IRQS
-*/
-#define BOARD_INFO
-/*#define PRINT_SPURIOUS*/
-
-/* AT697 Register MAP */
-static LEON_Register_Map *regs = (LEON_Register_Map *)0x80000000;
-
-/* initializes interrupt management for companionship board */
-void cchip1_irq_init(void);
-
-/* register interrupt handler (called from drivers) */
-void cchip1_set_isr(void *handler, int irqno, void *arg);
-
-#define READ_REG(address) _READ_REG((unsigned int)address)
-static __inline__ unsigned int _READ_REG(unsigned int addr) {
- unsigned int tmp;
- __asm__ ("lda [%1]1, %0 "
- : "=r"(tmp)
- : "r"(addr)
- );
- return tmp;
-}
-
-/* PCI bride reg layout on AMBA side */
-typedef struct {
- unsigned int bar0;
- unsigned int bar1;
- unsigned int bar2;
- unsigned int bar3;
- unsigned int bar4;/* 0x10 */
-
- unsigned int unused[4*3-1];
-
- unsigned int ambabars[1]; /* 0x40 */
-} amba_bridge_regs;
-
-/* PCI bride reg layout on PCI side */
-typedef struct {
- unsigned int bar0;
- unsigned int bar1;
- unsigned int bar2;
- unsigned int bar3;
- unsigned int bar4; /* 0x10 */
-
- unsigned int ilevel;
- unsigned int ipend;
- unsigned int iforce;
- unsigned int istatus;
- unsigned int iclear;
- unsigned int imask;
-} pci_bridge_regs;
-
-typedef struct {
- pci_bridge_regs *pcib;
- amba_bridge_regs *ambab;
-
- /* AT697 PCI */
- uint32_t bars[5];
- int bus, dev, fun;
-
- /* AMBA bus */
- struct ambapp_bus amba_bus;
- struct ambapp_mmap amba_maps[2];
-
- /* FT AHB SRAM */
- int ftsram_size; /* kb */
- unsigned int ftsram_start;
- unsigned int ftsram_end;
-
-} cchip1;
-
-cchip1 cc1;
-
-static int init_pcif(void)
-{
- uint32_t com1;
- int i,bus,dev,fun;
- pci_bridge_regs *pcib;
- amba_bridge_regs *ambab;
- struct ambapp_bus *abus;
-
- if ( BSP_pciFindDevice(0x1AC8, 0x0701, 0, &bus, &dev, &fun) == 0 ) {
- ;
- }else if (BSP_pciFindDevice(0x16E3, 0x0210, 0, &bus, &dev, &fun) == 0) {
- ;
- } else {
- /* didn't find any Companionship board on the PCI bus. */
- return -1;
- }
-
- /* found Companionship PCI board, Set it up: */
-
- pci_read_config_dword(bus, dev, fun, 0x10, &cc1.bars[0]);
- pci_read_config_dword(bus, dev, fun, 0x14, &cc1.bars[1]);
- pci_read_config_dword(bus, dev, fun, 0x18, &cc1.bars[2]);
- pci_read_config_dword(bus, dev, fun, 0x1c, &cc1.bars[3]);
- pci_read_config_dword(bus, dev, fun, 0x20, &cc1.bars[4]);
-
-#ifdef DEBUG
- for(i=0; i<5; i++){
- printk("PCI: BAR%d: 0x%x\n\r",i,cc1.bars[i]);
- }
-#endif
-
- /* Set up PCI ==> AMBA */
- pcib = (void *)cc1.bars[0];
- pcib->bar0 = 0xfc000000;
- /* pcib->bar1 = 0xff000000;*/
-#ifdef BOARD_INFO
- printk("Found CCHIP1 Board at 0x%lx\n\r",(unsigned int)pcib);
-#endif
-
- /* AMBA MAP cc1.bars[1] (in CPU) ==> 0xf0000000(remote amba address) */
- cc1.amba_maps[0].size = 0x04000000;
- cc1.amba_maps[0].local_adr = cc1.bars[1];
- cc1.amba_maps[0].remote_adr = 0xfc000000;
-
- /* Mark end of table */
- cc1.amba_maps[1].size=0;
- cc1.amba_maps[1].local_adr = 0;
- cc1.amba_maps[1].remote_adr = 0;
-
- /* Enable I/O and Mem accesses */
- pci_read_config_dword(bus, dev, fun, 0x4, &com1);
- com1 |= 0x3;
- pci_write_config_dword(bus, dev, fun, 0x4, com1);
- pci_read_config_dword(bus, dev, fun, 0x4, &com1);
-
- /* Set up AMBA Masters ==> PCI */
- ambab = (void *)(cc1.bars[1]+0x400);
-#ifdef DEBUG
- printk("AMBA: PCIBAR[%d]: 0x%x, 0x%x\n\r",0,ambab->bar0,pcib->bar0);
- printk("AMBA: PCIBAR[%d]: 0x%x, 0x%x\n\r",1,ambab->bar1,pcib->bar1);
- printk("AMBA: PCIBAR[%d]: 0x%x, 0x%x\n\r",2,ambab->bar2,pcib->bar2);
-#endif
- /* 0xe0000000(AMBA) ==> 0x40000000(PCI) ==> 0x40000000(AT697 AMBA) */
- ambab->ambabars[0] = 0x40000000;
-
- /* Scan bus for AMBA devices */
- abus = &cc1.amba_bus;
- memset(abus,0,sizeof(*abus));
- ambapp_scan(abus, cc1.bars[1]+0x3f00000, NULL, &cc1.amba_maps[0]);
-
- /* Init all msters, max 16 */
- for(i=1; i<16; i++) {
- ambab->ambabars[i] = 0x40000000;
- if (READ_REG(&ambab->ambabars[i]) != 0x40000000)
- break;
- }
-
- /* Enable PCI Master */
- pci_read_config_dword(bus, dev, fun, 0x4, &com1);
- com1 |= 0x4;
- pci_write_config_dword(bus, dev, fun, 0x4, com1);
- pci_read_config_dword(bus, dev, fun, 0x4, &com1);
-
- cc1.pcib = pcib;
- cc1.ambab = ambab;
- cc1.bus = bus;
- cc1.dev = dev;
- cc1.fun = fun;
-
- return 0;
-}
-
-#ifndef GAISLER_FTAHBRAM
- #define GAISLER_FTAHBRAM 0x50
-#endif
-static int init_onboard_sram(void)
-{
- struct ambapp_ahb_info ahb;
- struct ambapp_apb_info apb;
- unsigned int conf, size;
-
- /* Find SRAM controller
- * 1. AHB slave interface
- * 2. APB slave interface
- */
- if ( ambapp_find_apbslv(&cc1.amba_bus, VENDOR_GAISLER,
- GAISLER_FTAHBRAM, &apb) != 1 ){
- printk("On Board FT SRAM not found (APB)\n");
- return -1;
- }
-
- if ( ambapp_find_ahbslv(&cc1.amba_bus, VENDOR_GAISLER,
- GAISLER_FTAHBRAM, &ahb) != 1 ){
- printk("On Board FT SRAM not found (AHB)\n");
- return -1;
- }
-
- /* We have found the controller.
- * Get it going.
- *
- * Get size of SRAM
- */
- conf = *(unsigned int *)apb.start;
- size = (conf >>10) & 0x7;
-
- /* 2^x kb */
- cc1.ftsram_size = 1<<size;
- cc1.ftsram_start = ahb.start[0];
- cc1.ftsram_end = size*1024 + cc1.ftsram_start;
-#ifdef BOARD_INFO
- printk("Found FT AHB SRAM %dkb at 0x%lx\n",cc1.ftsram_size,cc1.ftsram_start);
-#endif
- return 0;
-}
-
-int cchip1_register(void)
-{
-
- /* Init AT697 PCI Controller */
- init_pci();
-
- /* Find & init CChip board .
- * Also scan AMBA Plug&Play info for us.
- */
- if ( init_pcif() ){
- printk("Failed to initialize CCHIP board\n\r");
- return -1;
- }
-
- /* Set interrupt common board stuff */
- cchip1_irq_init();
-
- /* Find on board SRAM */
- if ( init_onboard_sram() ){
- printk("Failed to register On Board SRAM. It is needed by b1553BRM\n");
- return -1;
- }
-
- /* Register interrupt install functions */
- b1553brm_pci_int_reg = cchip1_set_isr;
- occan_pci_int_reg = cchip1_set_isr;
- grspw_pci_int_reg = cchip1_set_isr;
- apbuart_pci_int_reg = cchip1_set_isr;
-
- /* register the BRM PCI driver, use 16k FTSRAM... */
- if ( b1553brm_pci_register(&cc1.amba_bus,0,0,3,cc1.ftsram_start,0xffa00000) ){
- printk("Failed to register BRM PCI driver\n");
- return -1;
- }
-
- /* register the BRM PCI driver, no DMA memory... */
- if ( occan_pci_register(&cc1.amba_bus) ){
- printk("Failed to register OC_CAN PCI driver\n");
- return -1;
- }
-
- /* register the GRSPW PCI driver, use malloc... */
- if ( grspw_pci_register(&cc1.amba_bus,0,0xe0000000) ){
- printk("Failed to register GRSPW PCI driver\n");
- return -1;
- }
-
- /* register the APBUART PCI driver, no DMA memory */
- if ( apbuart_pci_register(&cc1.amba_bus) ){
- printk("Failed to register APBUART PCI driver\n");
- return -1;
- }
-
- return 0;
-}
-
-static rtems_isr cchip1_interrupt_dispatcher(rtems_vector_number v);
-static unsigned int cchip1_spurious_cnt;
-
-typedef struct {
- unsigned int (*handler)(int irqno, void *arg);
- void *arg;
-} int_handler;
-
-static int_handler int_handlers[16];
-
-void cchip1_irq_init(void){
-
- /* Configure AT697 ioport bit 7 to input pci irq */
- regs->PIO_Direction &= ~(1<<7);
- regs->PIO_Interrupt = 0x87; /* level sensitive */
-
- /* Set up irq controller (mask all IRQs) */
- cc1.pcib->imask = 0x0000;
- cc1.pcib->ipend = 0;
- cc1.pcib->iclear = 0xffff;
- cc1.pcib->iforce = 0;
- cc1.pcib->ilevel = 0x0;
-
- memset(int_handlers,0,sizeof(int_handlers));
-
- /* Reset spurious counter */
- cchip1_spurious_cnt = 0;
-
- /* Register interrupt handler */
- set_vector(cchip1_interrupt_dispatcher,LEON_TRAP_TYPE(CCHIP_IRQ),1);
-}
-
-void cchip1_set_isr(void *handler, int irqno, void *arg){
- int_handlers[irqno].handler = handler;
- int_handlers[irqno].arg = arg;
-#ifdef DEBUG
- printk("Registering IRQ %d to 0x%lx(%d,0x%lx)\n\r",
- irqno,(unsigned int)handler,irqno,(unsigned int)arg);
-#endif
- cc1.pcib->imask |= 1<<irqno; /* Enable the registered IRQ */
-}
-
-static rtems_isr cchip1_interrupt_dispatcher(rtems_vector_number v){
- unsigned int pending = READ_REG(&cc1.pcib->ipend);
- unsigned int (*handler)(int irqno, void *arg);
- unsigned int clr = pending;
- int irq=1;
-
- if ( !pending ){
-#ifdef PRINT_SPURIOUS
- printk("Spurious IRQ %d: %d\n",v,cchip1_spurious_cnt);
-#endif
- cchip1_spurious_cnt++;
- return;
- }
-#ifdef DEBUG_IRQS
- printk("CCIRQ: 0x%x\n",(unsigned int)pending);
-#endif
- /* IRQ 0 doesn't exist */
- irq=1;
- pending = pending>>1;
-
- while ( pending ){
- if ( (pending & 1) && (handler=int_handlers[irq].handler) ){
- handler(irq,int_handlers[irq].arg);
- }
- irq++;
- pending = pending>>1;
- }
-
- cc1.pcib->iclear = clr;
-
- /*LEON_Clear_interrupt( brd->irq );*/
-}
diff --git a/c/src/lib/libbsp/sparc/leon2/include/cchip.h b/c/src/lib/libbsp/sparc/leon2/include/cchip.h
deleted file mode 100644
index d8d1e46..0000000
--- a/c/src/lib/libbsp/sparc/leon2/include/cchip.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/**
- * @defgroup cchip Companion Chip handler
- * @ingroup sparc_leon2
- *
- * @file
- *
- * @ingroup cchip
- *
- * @brief Register all drivers supported by the Companion Chip board
- */
-
-/*
- * COPYRIGHT (c) 2007.
- * Aeroflex Gaisler AB.
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#ifndef __CCHIP_H__
-#define __CCHIP_H__
-
-#include <b1553brm_pci.h>
-#include <occan_pci.h>
-#include <grspw_pci.h>
-#include <apbuart_pci.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define CCHIP_IRQ 4
-
-/* Register all drivers supported by the Companion Chip board */
-int cchip_register(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/c/src/lib/libbsp/sparc/leon2/include/rasta.h b/c/src/lib/libbsp/sparc/leon2/include/rasta.h
deleted file mode 100644
index b7eccb4..0000000
--- a/c/src/lib/libbsp/sparc/leon2/include/rasta.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/**
- * @defgroup leon2_rasta Rasta Handler
- * @ingroup sparc_leon2
- *
- * @file
- * @ingroup leon2_rasta
- * @brief Handles Rasta
- */
-
-/*
- * COPYRIGHT (c) 2007.
- * Aeroflex Gaisler AB.
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- *
- */
-
-#ifndef __RASTA_H__
-#define __RASTA_H__
-
-#include <bsp.h>
-
-#include <grcan.h>
-#include <b1553brm_rasta.h>
-#include <grspw.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-extern int rasta_register(void);
-
-/* Address of PCI bus on RASTA local AMBA bus */
-#define RASTA_PCI_BASE 0xe0000000
-
-/* Address of SRAM on RASTA local AMBA bus */
-#define RASTA_LOCAL_SRAM 0x40000000
-
-#define UART0_IRQNO 2
-#define UART1_IRQNO 3
-#define GRCAN_IRQNO 7
-#define SPW0_IRQNO 10
-#define SPW1_IRQNO 11
-#define SPW2_IRQNO 12
-#define BRM_IRQNO 13
-
-#define GRCAN_IRQ (3<<GRCAN_IRQNO)
-#define SPW0_IRQ (1<<SPW0_IRQNO)
-#define SPW1_IRQ (1<<SPW1_IRQNO)
-#define SPW2_IRQ (1<<SPW2_IRQNO)
-#define SPW_IRQ (7<<SPW0_IRQNO)
-#define BRM_IRQ (1<<BRM_IRQNO)
-#define UART0_IRQ (1<<UART0_IRQNO)
-#define UART1_IRQ (1<<UART1_IRQNO)
-
-/*
- * The following defines the bits in the UART Control Registers.
- *
- */
-#define LEON_REG_UART_CONTROL_RTD 0x000000FF /* RX/TX data */
-
-/*
- * The following defines the bits in the LEON UART Status Registers.
- */
-#define LEON_REG_UART_STATUS_DR 0x00000001 /* Data Ready */
-#define LEON_REG_UART_STATUS_TSE 0x00000002 /* TX Send Register Empty */
-#define LEON_REG_UART_STATUS_THE 0x00000004 /* TX Hold Register Empty */
-#define LEON_REG_UART_STATUS_BR 0x00000008 /* Break Error */
-#define LEON_REG_UART_STATUS_OE 0x00000010 /* RX Overrun Error */
-#define LEON_REG_UART_STATUS_PE 0x00000020 /* RX Parity Error */
-#define LEON_REG_UART_STATUS_FE 0x00000040 /* RX Framing Error */
-#define LEON_REG_UART_STATUS_ERR 0x00000078 /* Error Mask */
-
-
-/*
- * The following defines the bits in the LEON UART Status Registers.
- */
-#define LEON_REG_UART_CTRL_RE 0x00000001 /* Receiver enable */
-#define LEON_REG_UART_CTRL_TE 0x00000002 /* Transmitter enable */
-#define LEON_REG_UART_CTRL_RI 0x00000004 /* Receiver interrupt enable */
-#define LEON_REG_UART_CTRL_TI 0x00000008 /* Transmitter interrupt enable */
-#define LEON_REG_UART_CTRL_PS 0x00000010 /* Parity select */
-#define LEON_REG_UART_CTRL_PE 0x00000020 /* Parity enable */
-#define LEON_REG_UART_CTRL_FL 0x00000040 /* Flow control enable */
-#define LEON_REG_UART_CTRL_LB 0x00000080 /* Loop Back enable */
-
-#define UART_SET_SCALER 0
-#define UART_SET_CTRL 1
-#define UART_GET_STAT 2
-#define UART_CLR_STAT 3
-
-struct uart_reg {
- volatile unsigned int data; /* 0x00 */
- volatile unsigned int status; /* 0x04 */
- volatile unsigned int ctrl; /* 0x08 */
- volatile unsigned int scaler; /* 0x0C */
-};
-
-
-void uart_register(unsigned int baseaddr);
-rtems_device_driver uart_initialize(rtems_device_major_number major,
- rtems_device_minor_number minor, void *arg);
-rtems_device_driver uart_open(rtems_device_major_number major,
- rtems_device_minor_number minor, void *arg);
-rtems_device_driver uart_close(rtems_device_major_number major,
- rtems_device_minor_number minor, void *arg);
-rtems_device_driver uart_read(rtems_device_major_number major,
- rtems_device_minor_number minor, void *arg);
-rtems_device_driver uart_write(rtems_device_major_number major,
- rtems_device_minor_number minor, void *arg);
-rtems_device_driver uart_control(rtems_device_major_number major,
- rtems_device_minor_number minor, void *arg);
-
-
-struct gpio_reg {
- volatile unsigned int in_data; /* 0x00 */
- volatile unsigned int out_data; /* 0x04 */
- volatile unsigned int dir; /* 0x08 */
- volatile unsigned int imask; /* 0x0C */
- volatile unsigned int ipol; /* 0x10 */
- volatile unsigned int iedge; /* 0x14 */
-};
-
-extern struct gpio_reg *gpio0, *gpio1;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/c/src/lib/libbsp/sparc/leon2/preinstall.am b/c/src/lib/libbsp/sparc/leon2/preinstall.am
index 01b2ab9..ab2498d 100644
--- a/c/src/lib/libbsp/sparc/leon2/preinstall.am
+++ b/c/src/lib/libbsp/sparc/leon2/preinstall.am
@@ -45,66 +45,6 @@ $(PROJECT_INCLUDE)/tm27.h: include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/tm27.h
-$(PROJECT_INCLUDE)/rasta.h: include/rasta.h $(PROJECT_INCLUDE)/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rasta.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/rasta.h
-
-$(PROJECT_INCLUDE)/cchip.h: include/cchip.h $(PROJECT_INCLUDE)/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/cchip.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/cchip.h
-
-$(PROJECT_INCLUDE)/grspw.h: ../../sparc/shared/include/grspw.h $(PROJECT_INCLUDE)/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/grspw.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/grspw.h
-
-$(PROJECT_INCLUDE)/grspw_pci.h: ../../sparc/shared/include/grspw_pci.h $(PROJECT_INCLUDE)/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/grspw_pci.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/grspw_pci.h
-
-$(PROJECT_INCLUDE)/grspw_rasta.h: ../../sparc/shared/include/grspw_rasta.h $(PROJECT_INCLUDE)/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/grspw_rasta.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/grspw_rasta.h
-
-$(PROJECT_INCLUDE)/occan.h: ../../sparc/shared/include/occan.h $(PROJECT_INCLUDE)/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/occan.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/occan.h
-
-$(PROJECT_INCLUDE)/occan_pci.h: ../../sparc/shared/include/occan_pci.h $(PROJECT_INCLUDE)/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/occan_pci.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/occan_pci.h
-
-$(PROJECT_INCLUDE)/grcan.h: ../../sparc/shared/include/grcan.h $(PROJECT_INCLUDE)/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/grcan.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/grcan.h
-
-$(PROJECT_INCLUDE)/grcan_rasta.h: ../../sparc/shared/include/grcan_rasta.h $(PROJECT_INCLUDE)/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/grcan_rasta.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/grcan_rasta.h
-
-$(PROJECT_INCLUDE)/apbuart.h: ../../sparc/shared/include/apbuart.h $(PROJECT_INCLUDE)/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/apbuart.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/apbuart.h
-
-$(PROJECT_INCLUDE)/apbuart_pci.h: ../../sparc/shared/include/apbuart_pci.h $(PROJECT_INCLUDE)/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/apbuart_pci.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/apbuart_pci.h
-
-$(PROJECT_INCLUDE)/apbuart_rasta.h: ../../sparc/shared/include/apbuart_rasta.h $(PROJECT_INCLUDE)/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/apbuart_rasta.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/apbuart_rasta.h
-
-$(PROJECT_INCLUDE)/b1553brm.h: ../../sparc/shared/include/b1553brm.h $(PROJECT_INCLUDE)/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/b1553brm.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/b1553brm.h
-
-$(PROJECT_INCLUDE)/b1553brm_pci.h: ../../sparc/shared/include/b1553brm_pci.h $(PROJECT_INCLUDE)/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/b1553brm_pci.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/b1553brm_pci.h
-
-$(PROJECT_INCLUDE)/b1553brm_rasta.h: ../../sparc/shared/include/b1553brm_rasta.h $(PROJECT_INCLUDE)/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/b1553brm_rasta.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/b1553brm_rasta.h
-
$(PROJECT_INCLUDE)/debug_defs.h: ../../sparc/shared/include/debug_defs.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/debug_defs.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/debug_defs.h
@@ -169,6 +109,46 @@ $(PROJECT_INCLUDE)/tlib.h: ../../sparc/shared/include/tlib.h $(PROJECT_INCLUDE)/
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tlib.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/tlib.h
+$(PROJECT_INCLUDE)/grpci2.h: ../../sparc/shared/include/grpci2.h $(PROJECT_INCLUDE)/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/grpci2.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/grpci2.h
+
+$(PROJECT_INCLUDE)/gr_701.h: ../../sparc/shared/include/gr_701.h $(PROJECT_INCLUDE)/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/gr_701.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/gr_701.h
+
+$(PROJECT_INCLUDE)/gr_rasta_adcdac.h: ../../sparc/shared/include/gr_rasta_adcdac.h $(PROJECT_INCLUDE)/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/gr_rasta_adcdac.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/gr_rasta_adcdac.h
+
+$(PROJECT_INCLUDE)/gr_rasta_io.h: ../../sparc/shared/include/gr_rasta_io.h $(PROJECT_INCLUDE)/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/gr_rasta_io.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/gr_rasta_io.h
+
+$(PROJECT_INCLUDE)/gr_rasta_tmtc.h: ../../sparc/shared/include/gr_rasta_tmtc.h $(PROJECT_INCLUDE)/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/gr_rasta_tmtc.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/gr_rasta_tmtc.h
+
+$(PROJECT_INCLUDE)/b1553brm.h: ../../sparc/shared/include/b1553brm.h $(PROJECT_INCLUDE)/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/b1553brm.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/b1553brm.h
+
+$(PROJECT_INCLUDE)/occan.h: ../../sparc/shared/include/occan.h $(PROJECT_INCLUDE)/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/occan.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/occan.h
+
+$(PROJECT_INCLUDE)/grcan.h: ../../sparc/shared/include/grcan.h $(PROJECT_INCLUDE)/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/grcan.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/grcan.h
+
+$(PROJECT_INCLUDE)/grspw.h: ../../sparc/shared/include/grspw.h $(PROJECT_INCLUDE)/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/grspw.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/grspw.h
+
+$(PROJECT_INCLUDE)/apbuart.h: ../../sparc/shared/include/apbuart.h $(PROJECT_INCLUDE)/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/apbuart.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/apbuart.h
+
$(PROJECT_INCLUDE)/i2cmst.h: ../../sparc/shared/include/i2cmst.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/i2cmst.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/i2cmst.h
diff --git a/c/src/lib/libbsp/sparc/leon2/rasta/rasta.c b/c/src/lib/libbsp/sparc/leon2/rasta/rasta.c
deleted file mode 100644
index bfd9e31..0000000
--- a/c/src/lib/libbsp/sparc/leon2/rasta/rasta.c
+++ /dev/null
@@ -1,386 +0,0 @@
-/**
- * @file
- * @ingroup leon2_rasta
- * @brief GR-RASTA-IO PCI board driver
- */
-
-/*
- * GR-RASTA-IO PCI board driver
- *
- * COPYRIGHT (c) 2007.
- * Aeroflex Gaisler AB.
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- */
-
-#include <rtems/bspIo.h>
-#include <pci.h>
-#include <rasta.h>
-#include <ambapp.h>
-#include <grlib.h>
-#include <grcan_rasta.h>
-#include <grspw_rasta.h>
-#include <b1553brm_rasta.h>
-#include <apbuart_rasta.h>
-
-#include <string.h>
-
-/* If RASTA_SRAM is defined SRAM will be used, else SDRAM */
-/*#define RASTA_SRAM 1*/
-
-#define RASTA_IRQ 5
-
-/* Offset from 0x80000000 (dual bus version) */
-#define AHB1_IOAREA_BASE_ADDR 0x80100000
-#define APB2_OFFSET 0x200000
-#define IRQ_OFFSET 0x200500
-#define GRHCAN_OFFSET 0x201000
-#define BRM_OFFSET 0x100000
-#define SPW_OFFSET 0xa00
-#define UART_OFFSET 0x200200
-#define GPIO0_OFF 0x200600
-#define GPIO1_OFF 0x200700
-
-/* #define DEBUG 1 */
-
-#ifdef DEBUG
-#define DBG(x...) printk(x)
-#else
-#define DBG(x...)
-#endif
-
-static int bus, dev, fun;
-
-struct irqmp_regs *irq = NULL;
-LEON_Register_Map *regs = (LEON_Register_Map *)0x80000000;
-
-struct gpio_reg *gpio0, *gpio1;
-
-/* static rtems_isr pci_interrupt_handler (rtems_vector_number v) { */
-
-/* volatile unsigned int *pci_int = (volatile unsigned int *) 0x80000168;*/
-/* volatile unsigned int *pci_mem = (volatile unsigned int *) 0xb0400000;*/
-
-/* if (*pci_int & 0x20) { */
-
-/* *pci_int = 0x20; */
-
-/* *pci_mem = 0; */
-
-/* printk("pci died\n"); */
-
-/* } */
-
-/* } */
-
-void *uart0_int_arg, *uart1_int_arg;
-void *spw0_int_arg, *spw1_int_arg, *spw2_int_arg;
-void *grcan_int_arg;
-void *brm_int_arg;
-
-void (*uart0_int_handler)(int irq, void *arg) = NULL;
-void (*uart1_int_handler)(int irq, void *arg) = NULL;
-void (*spw0_int_handler)(int irq, void *arg) = NULL;
-void (*spw1_int_handler)(int irq, void *arg) = NULL;
-void (*spw2_int_handler)(int irq, void *arg) = NULL;
-void (*grcan_int_handler)(int irq, void *arg) = NULL;
-void (*brm_int_handler)(int irq, void *arg) = NULL;
-
-static rtems_isr rasta_interrupt_handler (rtems_vector_number v)
-{
- unsigned int status;
-
- status = irq->ipend;
-
- if ( (status & GRCAN_IRQ) && grcan_int_handler ) {
- grcan_int_handler(GRCAN_IRQNO,grcan_int_arg);
- }
-
- if (status & SPW_IRQ) {
- if ( (status & SPW0_IRQ) && spw0_int_handler ){
- spw0_int_handler(SPW0_IRQNO,spw0_int_arg);
- }
-
- if ( (status & SPW1_IRQ) && spw1_int_handler ){
- spw1_int_handler(SPW1_IRQNO,spw1_int_arg);
- }
-
- if ( (status & SPW2_IRQ) && spw2_int_handler ){
- spw2_int_handler(SPW2_IRQNO,spw2_int_arg);
- }
- }
- if ((status & BRM_IRQ) && brm_int_handler ){
- brm_int_handler(BRM_IRQNO,brm_int_arg);
- }
- if ( (status & UART0_IRQ) && uart0_int_handler ) {
- uart0_int_handler(UART0_IRQNO,uart0_int_arg);
- }
- if ( (status & UART1_IRQ) && uart1_int_handler) {
- uart1_int_handler(UART1_IRQNO,uart1_int_arg);
- }
-
- DBG("RASTA-IRQ: 0x%x\n",status);
- irq->iclear = status;
-
-}
-
-static void rasta_interrrupt_register(void *handler, int irqno, void *arg)
-{
- DBG("RASTA: Registering irq %d\n",irqno);
- if ( irqno == UART0_IRQNO ){
- DBG("RASTA: Registering uart0 handler: 0x%x, arg: 0x%x\n",handler,arg);
- uart0_int_handler = handler;
- uart0_int_arg = arg;
-
- /* unmask interrupt source */
- irq->iclear = UART0_IRQ;
- irq->mask[0] |= UART0_IRQ;
- }
-
- if ( irqno == UART1_IRQNO ){
- DBG("RASTA: Registering uart1 handler: 0x%x, arg: 0x%x\n",handler,arg);
- uart1_int_handler = handler;
- uart1_int_arg = arg;
-
- /* unmask interrupt source */
- irq->iclear = UART1_IRQ;
- irq->mask[0] |= UART1_IRQ;
- }
-
- if ( irqno == SPW0_IRQNO ){
- DBG("RASTA: Registering spw0 handler: 0x%x, arg: 0x%x\n",handler,arg);
- spw0_int_handler = handler;
- spw0_int_arg = arg;
-
- /* unmask interrupt source */
- irq->iclear = SPW0_IRQ;
- irq->mask[0] |= SPW0_IRQ;
- }
-
- if ( irqno == SPW1_IRQNO ){
- DBG("RASTA: Registering spw1 handler: 0x%x, arg: 0x%x\n",handler,arg);
- spw1_int_handler = handler;
- spw1_int_arg = arg;
-
- /* unmask interrupt source */
- irq->iclear = SPW1_IRQ;
- irq->mask[0] |= SPW1_IRQ;
- }
-
- if ( irqno == SPW2_IRQNO ){
- DBG("RASTA: Registering spw2 handler: 0x%x, arg: 0x%x\n",handler,arg);
- spw2_int_handler = handler;
- spw2_int_arg = arg;
-
- /* unmask interrupt source */
- irq->iclear = SPW2_IRQ;
- irq->mask[0] |= SPW2_IRQ;
- }
-
- if ( irqno == GRCAN_IRQNO ){
- DBG("RASTA: Registering GRCAN handler: 0x%x, arg: 0x%x\n",handler,arg);
- grcan_int_handler = handler;
- grcan_int_arg = arg;
-
- /* unmask interrupt source */
- irq->iclear = GRCAN_IRQ;
- irq->mask[0] |= GRCAN_IRQ;
- }
-
- if ( irqno == BRM_IRQNO ){
- DBG("RASTA: Registering BRM handler: 0x%x, arg: 0x%x\n",handler,arg);
- brm_int_handler = handler;
- brm_int_arg = arg;
-
- /* unmask interrupt source */
- irq->iclear = BRM_IRQ;
- irq->mask[0] |= BRM_IRQ;
- }
-}
-
-
-static int rasta_get_gpio(
- struct ambapp_bus *abus, int index, struct gpio_reg **regs,
- int *irq)
-{
- struct ambapp_apb_info dev;
- int cores;
-
- if ( !abus )
- return -1;
-
- /* Scan PnP info for GPIO port number 'index' */
- cores = ambapp_find_apbslv_next(abus, VENDOR_GAISLER, GAISLER_GPIO, &dev,
- index);
- if ( cores < 1 )
- return -1;
-
- if ( regs )
- *regs = (struct gpio_reg *)dev.start;
-
- if ( irq )
- *irq = dev.irq;
-
- return 0;
-}
-
-/* AMBA Plug&Play information */
-static struct ambapp_bus abus;
-static struct ambapp_mmap amba_maps[3];
-
-int rasta_register(void)
-{
- uint32_t bar0, bar1, data;
-
- unsigned int *page0 = NULL;
- unsigned int *apb_base = NULL;
- int found=0;
-
-
- DBG("Searching for RASTA board ...");
-
- /* Search PCI vendor/device id. */
- if (BSP_pciFindDevice(0x1AC8, 0x0010, 0, &bus, &dev, &fun) == 0) {
- found = 1;
- }
-
- /* Search old PCI vendor/device id. */
- if ( (!found) &&
- (BSP_pciFindDevice(0x16E3, 0x0210, 0, &bus, &dev, &fun) == 0) ) {
- found = 1;
- }
-
- /* Did we find a RASTA board? */
- if ( !found )
- return -1;
-
- DBG(" found it (dev/fun: %d/%d).\n", dev, fun);
-
- pci_read_config_dword(bus, dev, fun, 0x10, &bar0);
- pci_read_config_dword(bus, dev, fun, 0x14, &bar1);
-
- page0 = (unsigned int *)(bar0 + 0x400000);
- *page0 = 0x80000000; /* Point PAGE0 to start of APB */
-
- apb_base = (unsigned int *)(bar0+APB2_OFFSET);
-
-/* apb_base[0] = 0x000002ff;
- apb_base[1] = 0x8a205260;
- apb_base[2] = 0x00184000; */
-
- /* Configure memory controller */
-#ifdef RASTA_SRAM
- apb_base[0] = 0x000002ff;
- apb_base[1] = 0x00001260;
- apb_base[2] = 0x000e8000;
-#else
- apb_base[0] = 0x000002ff;
- apb_base[1] = 0x82206000;
- apb_base[2] = 0x000e8000;
-#endif
- /* Set up rasta irq controller */
- irq = (struct irqmp_regs *) (bar0+IRQ_OFFSET);
- irq->iclear = 0xffff;
- irq->ilevel = 0;
- irq->mask[0] = 0xffff &
- ~(UART0_IRQ|UART1_IRQ|SPW0_IRQ|SPW1_IRQ|SPW2_IRQ|GRCAN_IRQ|BRM_IRQ);
-
- /* Configure AT697 ioport bit 7 to input pci irq */
- regs->PIO_Direction &= ~(1<<7);
- regs->PIO_Interrupt |= (0x87<<8); /* level sensitive */
-
- apb_base[0x100] |= 0x40000000; /* Set GRPCI mmap 0x4 */
- apb_base[0x104] = 0x40000000; /* 0xA0000000; Point PAGE1 to RAM */
-
-
- /* set parity error response */
- pci_read_config_dword(bus, dev, fun, 0x4, &data);
- pci_write_config_dword(bus, dev, fun, 0x4, data|0x40);
-
-
- pci_master_enable(bus, dev, fun);
-
- /* install PCI interrupt vector */
- /* set_vector(pci_interrupt_handler,14+0x10, 1); */
-
-
- /* install interrupt vector */
- set_vector(rasta_interrupt_handler, RASTA_IRQ+0x10, 1);
-
- /* Scan AMBA Plug&Play */
-
- /* AMBA MAP bar0 (in CPU) ==> 0x80000000(remote amba address) */
- amba_maps[0].size = 0x10000000;
- amba_maps[0].local_adr = bar0;
- amba_maps[0].remote_adr = 0x80000000;
-
- /* AMBA MAP bar1 (in CPU) ==> 0x40000000(remote amba address) */
- amba_maps[1].size = 0x10000000;
- amba_maps[1].local_adr = bar1;
- amba_maps[1].remote_adr = 0x40000000;
-
- /* Mark end of table */
- amba_maps[2].size=0;
- amba_maps[2].local_adr = 0;
- amba_maps[2].remote_adr = 0;
-
- memset(&abus,0,sizeof(abus));
-
- /* Start AMBA PnP scan at first AHB bus */
- ambapp_scan(&abus, bar0 + (AHB1_IOAREA_BASE_ADDR & ~0xf0000000), NULL,
- &amba_maps[0]);
-
- printk("Registering RASTA GRCAN driver\n\r");
-
- /*grhcan_register(bar0 + GRHCAN_OFFSET, bar1);*/
- grcan_rasta_int_reg=rasta_interrrupt_register;
- if ( grcan_rasta_ram_register(&abus,bar1+0x20000) ){
- printk("Failed to register RASTA GRCAN driver\n\r");
- return -1;
- }
-
- printk("Registering RASTA BRM driver\n\r");
-
- /*brm_register(bar0 + BRM_OFFSET, bar1);*/
- /* register the BRM RASTA driver, use 128k on RASTA SRAM... */
- b1553brm_rasta_int_reg=rasta_interrrupt_register;
- if ( b1553brm_rasta_register(&abus,2,0,3,bar1,0x40000000) ){
- printk("Failed to register BRM RASTA driver\n");
- return -1;
- }
-
- /* provide the spacewire driver with AMBA Plug&Play
- * info so that it can find the GRSPW cores.
- */
- grspw_rasta_int_reg=rasta_interrrupt_register;
- if ( grspw_rasta_register(&abus,bar1) ){
- printk("Failed to register RASTA GRSPW driver\n\r");
- return -1;
- }
-
- /* provide the spacewire driver with AMBA Plug&Play
- * info so that it can find the GRSPW cores.
- */
- apbuart_rasta_int_reg=rasta_interrrupt_register;
- if ( apbuart_rasta_register(&abus) ){
- printk("Failed to register RASTA APBUART driver\n\r");
- return -1;
- }
-
- /* Find GPIO0 address */
- if ( rasta_get_gpio(&abus,0,&gpio0,NULL) ){
- printk("Failed to get address for RASTA GPIO0\n\r");
- return -1;
- }
-
- /* Find GPIO1 address */
- if ( rasta_get_gpio(&abus,1,&gpio1,NULL) ){
- printk("Failed to get address for RASTA GPIO1\n\r");
- return -1;
- }
-
- /* Successfully registered the RASTA board */
- return 0;
-}
diff --git a/c/src/lib/libbsp/sparc/leon3/Makefile.am b/c/src/lib/libbsp/sparc/leon3/Makefile.am
index a451208..dee5d57 100644
--- a/c/src/lib/libbsp/sparc/leon3/Makefile.am
+++ b/c/src/lib/libbsp/sparc/leon3/Makefile.am
@@ -109,30 +109,37 @@ libbsp_a_SOURCES += ../../sparc/shared/pci/pcif.c
libbsp_a_SOURCES += ../../sparc/shared/pci/pci_memreg_sparc_le.c
libbsp_a_SOURCES += ../../sparc/shared/pci/pci_memreg_sparc_be.c
+# PCI target devices
+include_HEADERS += ../../sparc/shared/include/gr_701.h
+include_HEADERS += ../../sparc/shared/include/gr_rasta_adcdac.h
+include_HEADERS += ../../sparc/shared/include/gr_rasta_io.h
+include_HEADERS += ../../sparc/shared/include/gr_rasta_tmtc.h
+include_HEADERS += ../../sparc/shared/include/gr_tmtc_1553.h
+libbsp_a_SOURCES += ../../sparc/shared/pci/gr_701.c
+libbsp_a_SOURCES += ../../sparc/shared/pci/gr_rasta_adcdac.c
+libbsp_a_SOURCES += ../../sparc/shared/pci/gr_rasta_io.c
+libbsp_a_SOURCES += ../../sparc/shared/pci/gr_rasta_spw_router.c
+libbsp_a_SOURCES += ../../sparc/shared/pci/gr_rasta_tmtc.c
+libbsp_a_SOURCES += ../../sparc/shared/pci/gr_tmtc_1553.c
+
# B1553BRM
-include_HEADERS += ../../sparc/shared/include/b1553brm.h \
- ../../sparc/shared/include/b1553brm_pci.h
-libbsp_a_SOURCES += ../../sparc/shared/1553/b1553brm.c \
- ../../sparc/shared/1553/b1553brm_pci.c
+include_HEADERS += ../../sparc/shared/include/b1553brm.h
+libbsp_a_SOURCES += ../../sparc/shared/1553/b1553brm.c
# CAN
include_HEADERS += ../../sparc/shared/include/occan.h \
- ../../sparc/shared/include/occan_pci.h ../../sparc/shared/include/grcan.h
+ ../../sparc/shared/include/grcan.h
libbsp_a_SOURCES += ../../sparc/shared/can/occan.c \
- ../../sparc/shared/can/occan_pci.c ../../sparc/shared/can/grcan.c
+ ../../sparc/shared/can/grcan.c
# SpaceWire
-include_HEADERS += ../../sparc/shared/include/grspw.h \
- ../../sparc/shared/include/grspw_pci.h
-libbsp_a_SOURCES += ../../sparc/shared/spw/grspw.c \
- ../../sparc/shared/spw/grspw_pci.c
+include_HEADERS += ../../sparc/shared/include/grspw.h
+libbsp_a_SOURCES += ../../sparc/shared/spw/grspw.c
# UART
include_HEADERS += ../../sparc/shared/include/apbuart.h \
- ../../sparc/shared/include/apbuart_pci.h \
../../sparc/shared/include/apbuart_termios.h
libbsp_a_SOURCES += ../../sparc/shared/uart/apbuart.c \
- ../../sparc/shared/uart/apbuart_pci.c \
../../sparc/shared/uart/apbuart_termios.c
# I2CMST
diff --git a/c/src/lib/libbsp/sparc/leon3/preinstall.am b/c/src/lib/libbsp/sparc/leon3/preinstall.am
index a12563a..631a7f0 100644
--- a/c/src/lib/libbsp/sparc/leon3/preinstall.am
+++ b/c/src/lib/libbsp/sparc/leon3/preinstall.am
@@ -129,22 +129,34 @@ $(PROJECT_INCLUDE)/grpci2.h: ../../sparc/shared/include/grpci2.h $(PROJECT_INCLU
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/grpci2.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/grpci2.h
+$(PROJECT_INCLUDE)/gr_701.h: ../../sparc/shared/include/gr_701.h $(PROJECT_INCLUDE)/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/gr_701.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/gr_701.h
+
+$(PROJECT_INCLUDE)/gr_rasta_adcdac.h: ../../sparc/shared/include/gr_rasta_adcdac.h $(PROJECT_INCLUDE)/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/gr_rasta_adcdac.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/gr_rasta_adcdac.h
+
+$(PROJECT_INCLUDE)/gr_rasta_io.h: ../../sparc/shared/include/gr_rasta_io.h $(PROJECT_INCLUDE)/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/gr_rasta_io.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/gr_rasta_io.h
+
+$(PROJECT_INCLUDE)/gr_rasta_tmtc.h: ../../sparc/shared/include/gr_rasta_tmtc.h $(PROJECT_INCLUDE)/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/gr_rasta_tmtc.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/gr_rasta_tmtc.h
+
+$(PROJECT_INCLUDE)/gr_tmtc_1553.h: ../../sparc/shared/include/gr_tmtc_1553.h $(PROJECT_INCLUDE)/$(dirstamp)
+ $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/gr_tmtc_1553.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/gr_tmtc_1553.h
+
$(PROJECT_INCLUDE)/b1553brm.h: ../../sparc/shared/include/b1553brm.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/b1553brm.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/b1553brm.h
-$(PROJECT_INCLUDE)/b1553brm_pci.h: ../../sparc/shared/include/b1553brm_pci.h $(PROJECT_INCLUDE)/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/b1553brm_pci.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/b1553brm_pci.h
-
$(PROJECT_INCLUDE)/occan.h: ../../sparc/shared/include/occan.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/occan.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/occan.h
-$(PROJECT_INCLUDE)/occan_pci.h: ../../sparc/shared/include/occan_pci.h $(PROJECT_INCLUDE)/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/occan_pci.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/occan_pci.h
-
$(PROJECT_INCLUDE)/grcan.h: ../../sparc/shared/include/grcan.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/grcan.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/grcan.h
@@ -153,18 +165,10 @@ $(PROJECT_INCLUDE)/grspw.h: ../../sparc/shared/include/grspw.h $(PROJECT_INCLUDE
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/grspw.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/grspw.h
-$(PROJECT_INCLUDE)/grspw_pci.h: ../../sparc/shared/include/grspw_pci.h $(PROJECT_INCLUDE)/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/grspw_pci.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/grspw_pci.h
-
$(PROJECT_INCLUDE)/apbuart.h: ../../sparc/shared/include/apbuart.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/apbuart.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/apbuart.h
-$(PROJECT_INCLUDE)/apbuart_pci.h: ../../sparc/shared/include/apbuart_pci.h $(PROJECT_INCLUDE)/$(dirstamp)
- $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/apbuart_pci.h
-PREINSTALL_FILES += $(PROJECT_INCLUDE)/apbuart_pci.h
-
$(PROJECT_INCLUDE)/apbuart_termios.h: ../../sparc/shared/include/apbuart_termios.h $(PROJECT_INCLUDE)/$(dirstamp)
$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/apbuart_termios.h
PREINSTALL_FILES += $(PROJECT_INCLUDE)/apbuart_termios.h
diff --git a/c/src/lib/libbsp/sparc/shared/1553/b1553brm_pci.c b/c/src/lib/libbsp/sparc/shared/1553/b1553brm_pci.c
deleted file mode 100644
index 2ae4af5..0000000
--- a/c/src/lib/libbsp/sparc/shared/1553/b1553brm_pci.c
+++ /dev/null
@@ -1,135 +0,0 @@
-#include <ambapp.h>
-#include <b1553brm_pci.h>
-
-/* Select PCI driver */
-#define B1553BRM_NO_AMBA
-#define B1553BRM_PCI
-
-#undef B1553BRM_MAXDEVS
-
-/* Use only 16K memory */
-#define DMA_MEM_16K
-
-/* Malloced memory or
- * Card local memory
- */
-#define B1553BRM_LOCAL_MEM
-
-#define DONT_DEF_RAMON
-
-/* memory must be aligned to a 128k boundary */
-unsigned int brmpci_memarea_address;
-#define B1553BRM_LOCAL_MEM_ADR brmpci_memarea_address
-
-/* We have custom address tranlation for HW addresses */
-#define B1553BRM_ADR_TO
-
-/* No custom MEMAREA=>CPU used since BRM Core work with offsets
- * in it's descriptors.
- */
-#undef B1553BRM_ADR_FROM
-
-/* Set registered device name */
-#define B1553BRM_DEVNAME "/dev/brmpci0"
-#define B1553BRM_DEVNAME_NO(devstr,no) ((devstr)[11]='0'+(no))
-
-/* Any non-static function will begin with */
-#define B1553BRM_PREFIX(name) b1553brmpci##name
-
-/* do nothing, assume that the interrupt handler is called
- * setup externally calling b1553_interrupt_handler.
- */
-#define B1553BRM_REG_INT(handler,irq,arg) \
- if ( b1553brm_pci_int_reg ) \
- b1553brm_pci_int_reg(handler,irq,arg);
-
-
-#ifdef B1553BRM_ADR_TO
-/* Translate a address within the Memory Region (memarea) into an Hardware
- * device address. This address is put into hardware registers or descriptors
- * so that the hardware can access the Memory Region.
- * Example:
- * An local AMBA access at 0xe0000000 will translate into PCI address 0x40000000,
- * the PCI address 0x40000000 will translate into CPU-AMBA address 0x40000000.
- */
-unsigned int brmpci_hw_address;
-static inline unsigned int memarea_to_hw(unsigned int addr) {
- /* don't translate? */
- if ( brmpci_hw_address == 0xffffffff )
- return addr;
- return ((addr & 0x000fffff) | brmpci_hw_address);
-}
-#endif
-
-/* not used since BRM Core work with offsets */
-#ifdef B1553BRM_ADR_FROM
-unsigned int brmpci_cpu_access_address;
-static inline unsigned int hw_to_cpu(unsigned int addr) {
- /* don't translate? */
- if ( brmpci_cpu_address == 0xffffffff )
- return addr;
- return ((addr & 0x0fffffff) | brmpci_cpu_address);
-}
-#endif
-
-void (*b1553brm_pci_int_reg)(void *handler, int irq, void *arg) = 0;
-
-static void b1553brmpci_interrupt_handler(int irq, void *arg);
-
-#include "b1553brm.c"
-
-/*
- *
- * memarea = preallocated memory somewhere, pointer to start of memory.
- * hw_address = how to translate a memarea address into an HW device AMBA address.
- */
-
-int b1553brm_pci_register(
- struct ambapp_bus *bus,
- unsigned int clksel,
- unsigned int clkdiv,
- unsigned int brm_freq,
- unsigned int memarea,
- unsigned int hw_address
- )
-{
- /* Setup configuration */
-
- /* if zero malloc will be used */
- brmpci_memarea_address = memarea;
-
- brmpci_hw_address = hw_address;
-
-#ifdef B1553BRM_ADR_FROM
- brmpci_cpu_address = memarea & 0xf0000000;
-#endif
-
- /* Register the driver */
- return B1553BRM_PREFIX(_register)(bus,clksel,clkdiv,brm_freq);
-}
-
-/* Call this from PCI interrupt handler
- * irq = the irq number of the HW device local to that IRQMP controller
- *
- */
-static void b1553brmpci_interrupt_handler(int irq, void *arg){
- brm_interrupt(arg);
-}
-
-#if 0
-int b1553brm_pci_interrupt_handler(int irqmask){
- int i;
- unsigned int mask=0;
- /* find minor */
- for(i=0; i<brm_cores; i++){
- if ( (1<<brms[i].irqno) & irqmask ){
- mask |= 1<<brms[i].irqno;
- brm_interrupt(&brms[i]);
- /* more interrupts to scan for? */
- if ( irqmask & ~mask )
- return mask; /* handled */
- }
- }
- return mask;
-}
-#endif
diff --git a/c/src/lib/libbsp/sparc/shared/1553/b1553brm_rasta.c b/c/src/lib/libbsp/sparc/shared/1553/b1553brm_rasta.c
deleted file mode 100644
index d15881e..0000000
--- a/c/src/lib/libbsp/sparc/shared/1553/b1553brm_rasta.c
+++ /dev/null
@@ -1,117 +0,0 @@
-/* Select PCI driver */
-#define B1553BRM_NO_AMBA
-#define B1553BRM_PCI
-
-#undef B1553BRM_MAXDEVS
-
-/* Use only 16K memory */
-#define DMA_MEM_128K
-
-/* Malloced memory or
- * Card local memory
- */
-#define B1553BRM_LOCAL_MEM
-
-#define DONT_DEF_RAMON
-
-/* memory must be aligned to a 128k boundary */
-unsigned int brmrasta_memarea_address;
-#define B1553BRM_LOCAL_MEM_ADR brmrasta_memarea_address
-
-/* We have custom address tranlation for HW addresses */
-#define B1553BRM_ADR_TO
-
-/* No custom MEMAREA=>CPU used since BRM Core work with offsets
- * in it's descriptors.
- */
-#undef B1553BRM_ADR_FROM
-
-/* Set registered device name */
-#define B1553BRM_DEVNAME "/dev/brmrasta0"
-#define B1553BRM_DEVNAME_NO(devstr,no) ((devstr)[13]='0'+(no))
-
-/* Any non-static function will begin with */
-#define B1553BRM_PREFIX(name) b1553brmrasta##name
-
-/* do nothing, assume that the interrupt handler is called
- * setup externally calling b1553_interrupt_handler.
- */
-#define B1553BRM_REG_INT(handler,irq,arg) \
- if ( b1553brm_rasta_int_reg ) \
- b1553brm_rasta_int_reg(handler,irq,arg);
-
-
-#ifdef B1553BRM_ADR_TO
-/* Translate a address within the Memory Region (memarea) into an Hardware
- * device address. This address is put into hardware registers or descriptors
- * so that the hardware can access the Memory Region.
- * Example:
- * An local AMBA access at 0xe0000000 will translate into PCI address 0x40000000,
- * the PCI address 0x40000000 will translate into CPU-AMBA address 0x40000000.
- */
-unsigned int brmrasta_hw_address;
-static inline unsigned int memarea_to_hw(unsigned int addr) {
- /* don't translate? */
- if ( brmrasta_hw_address == 0xffffffff )
- return addr;
- return ((addr & 0x0fffffff) | brmrasta_hw_address);
-}
-#endif
-
-/* not used since BRM Core work with offsets */
-#ifdef B1553BRM_ADR_FROM
-unsigned int brmrasta_cpu_access_address;
-static inline unsigned int hw_to_cpu(unsigned int addr) {
- /* don't translate? */
- if ( brmrasta_cpu_address == 0xffffffff )
- return addr;
- return ((addr & 0x0fffffff) | brmrasta_cpu_address);
-}
-#endif
-
-void (*b1553brm_rasta_int_reg)(void *handler, int irq, void *arg) = 0;
-
-static void b1553brmrasta_interrupt_handler(int irq, void *arg);
-
-#include "b1553brm.c"
-#include <b1553brm_rasta.h>
-
-
-/*
- *
- * memarea = preallocated memory somewhere, pointer to start of memory.
- * hw_address = how to translate a memarea address into an HW device AMBA address.
- */
-
-int b1553brm_rasta_register(
- struct ambapp_bus *bus,
- unsigned int clksel,
- unsigned int clkdiv,
- unsigned int brm_freq,
- unsigned int memarea,
- unsigned int hw_address
- )
-{
- /* Setup configuration */
-
- /* if zero the malloc will be used */
- brmrasta_memarea_address = memarea;
-
- brmrasta_hw_address = hw_address;
-
-#ifdef B1553BRM_ADR_FROM
- brmrasta_cpu_address = memarea & 0xf0000000;
-#endif
-
- /* Register the driver */
- return B1553BRM_PREFIX(_register)(bus,clksel,clkdiv,brm_freq);
-}
-
-/* Call this from RASTA interrupt handler
- * irq = the irq number of the HW device local to that IRQMP controller
- *
- */
-static void b1553brmrasta_interrupt_handler(int irq, void *arg){
- brm_interrupt(arg);
-}
-
diff --git a/c/src/lib/libbsp/sparc/shared/can/grcan_rasta.c b/c/src/lib/libbsp/sparc/shared/can/grcan_rasta.c
deleted file mode 100644
index 8832e09..0000000
--- a/c/src/lib/libbsp/sparc/shared/can/grcan_rasta.c
+++ /dev/null
@@ -1,100 +0,0 @@
-#include <rasta.h>
-#include <grcan_rasta.h>
-
-/* PCI frequency */
-#define SYS_FREQ_HZ 30000000
-
-/*#define USE_AT697_RAM 1 */
-
-/* memarea_to_hw(x)
- *
- * x: address in AT697 address space
- *
- * returns the address in the RASTA address space that can be used to access x with dma.
- *
-*/
-#ifdef USE_AT697_RAM
-static inline unsigned int memarea_to_hw(unsigned int addr) {
- return ((addr & 0x0fffffff) | RASTA_PCI_BASE);
-}
-#else
-static inline unsigned int memarea_to_hw(unsigned int addr) {
- return ((addr & 0x0fffffff) | RASTA_LOCAL_SRAM);
-}
-#endif
-
-#define MEMAREA_TO_HW(x) memarea_to_hw(x)
-
-#define IRQ_CLEAR_PENDING(irqno)
-#define IRQ_UNMASK(irqno)
-#define IRQ_MASK(irqno)
-
-#define IRQ_GLOBAL_PREPARE(level) rtems_interrupt_level level
-#define IRQ_GLOBAL_DISABLE(level) rtems_interrupt_disable(level)
-#define IRQ_GLOBAL_ENABLE(level) rtems_interrupt_enable(level)
-
-#define GRCAN_REG_INT(handler,irqno,arg) \
- if ( grcan_rasta_int_reg ) \
- grcan_rasta_int_reg(handler,irqno,arg);
-
-void (*grcan_rasta_int_reg)(void *handler, int irq, void *arg) = 0;
-
-#define GRCAN_PREFIX(name) grcan_rasta##name
-
-/* We provide our own handler */
-#define GRCAN_DONT_DECLARE_IRQ_HANDLER
-
-#define GRCAN_REG_BYPASS_CACHE
-#define GRCAN_DMA_BYPASS_CACHE
-
-#define GRCAN_MAX_CORES 1
-
-/* Custom Statically allocated memory */
-#undef STATICALLY_ALLOCATED_TX_BUFFER
-#undef STATICALLY_ALLOCATED_RX_BUFFER
-
-#define STATIC_TX_BUF_SIZE 4096
-#define STATIC_RX_BUF_SIZE 4096
-#define TX_BUF_SIZE 4096
-#define RX_BUF_SIZE 4096
-
-#define STATIC_TX_BUF_ADDR(core) \
- ((unsigned int *)\
- (grcan_rasta_rambase+(core)*(STATIC_TX_BUF_SIZE+STATIC_RX_BUF_SIZE)))
-
-#define STATIC_RX_BUF_ADDR(core) \
- ((unsigned int *) \
- (grcan_rasta_rambase+(core)*(STATIC_TX_BUF_SIZE+STATIC_RX_BUF_SIZE)+STATIC_RX_BUF_SIZE))
-
-
-#define GRCAN_DEVNAME "/dev/grcan0"
-#define GRCAN_DEVNAME_NO(devstr,no) ((devstr)[10]='0'+(no))
-
-void grcan_rasta_interrupt_handler(int irq, void *pDev);
-
-unsigned int grcan_rasta_rambase;
-
-#include "grcan.c"
-
-
-int grcan_rasta_ram_register(struct ambapp_bus *abus, int rambase)
-{
- grcan_rasta_rambase = rambase;
-
- return GRCAN_PREFIX(_register)(abus);
-}
-#if 0
-static void grcan_rasta_interrupt_handler(int v)
-{
- /* We know there is always only one GRCAN core in a RASTA chip... */
- grcan_interrupt(&grcans[0]);
- /*
- struct grcan_priv *pDev = arg;
- grcan_interrupt(pDev);
- */
-}
-#endif
-void GRCAN_PREFIX(_interrupt_handler)(int irq, void *pDev)
-{
- grcan_interrupt(pDev);
-}
diff --git a/c/src/lib/libbsp/sparc/shared/can/occan_pci.c b/c/src/lib/libbsp/sparc/shared/can/occan_pci.c
deleted file mode 100644
index 12273c9..0000000
--- a/c/src/lib/libbsp/sparc/shared/can/occan_pci.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/* PCI cannot do byte accesses to addresses aligned byte wise
- * Use alternative reg map.
- */
-#define OCCAN_WORD_REGS
-
-#include <occan_pci.h>
-
-/* Set registered device name */
-#define OCCAN_DEVNAME "/dev/occanpci0"
-#define OCCAN_DEVNAME_NO(devstr,no) ((devstr)[13]='0'+(no))
-
-/* Any non-static function will begin with */
-#define OCCAN_PREFIX(name) occanpci##name
-
-/* do nothing, assume that the interrupt handler is called
- * setup externally calling b1553_interrupt_handler.
- */
-#define OCCAN_REG_INT(handler,irq,arg) \
- if ( occan_pci_int_reg ) \
- occan_pci_int_reg(handler,irq,arg);
-
-void (*occan_pci_int_reg)(void *handler, int irq, void *arg) = 0;
-
-void occanpci_interrupt_handler(int irq, void *arg);
-
-/* AMBA Bus is clocked using the PCI clock (33.3MHz) */
-#define SYS_FREQ_HZ 33333333
-
-/* Enable two redundant channels */
-#define REDUNDANT_CHANNELS 2
-
-#define OCCAN_SET_CHANNEL(priv,channel) occanpci_set_channel(priv,channel)
-
-#include "occan.c"
-
-/* Define method that sets redundant channel
- * The channel select register:
- * 0x00 = byte regs
- * 0x40 = channel select
- * 0x80 = word regs
- */
-static void inline occanpci_set_channel(occan_priv *priv, int channel){
- unsigned int *chan_sel = (unsigned int *)(((unsigned int)priv->regs & ~0xff)+0x40);
- if ( channel == 0 )
- *chan_sel = 0;
- else
- *chan_sel = 0xffffffff;
-}
-
-int occan_pci_register(struct ambapp_bus *bus)
-{
- /* Setup configuration */
-
- /* Register the driver */
- return OCCAN_PREFIX(_register)(bus);
-}
-
-
-/* Call this from PCI interrupt handler
- * irq = the irq number of the HW device local to that IRQMP controller
- *
- */
-void occanpci_interrupt_handler(int irq, void *arg){
- occan_interrupt(arg);
-}
diff --git a/c/src/lib/libbsp/sparc/shared/include/apbuart_pci.h b/c/src/lib/libbsp/sparc/shared/include/apbuart_pci.h
deleted file mode 100644
index d2d8bf0..0000000
--- a/c/src/lib/libbsp/sparc/shared/include/apbuart_pci.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/**
- * @file
- * @ingroup uart
- * @brief APBUART via PCI - driver interface
- */
-
-/*
- * COPYRIGHT (c) 2007.
- * Gaisler Research
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- *
- */
-
-#ifndef __APBUART_PCI_H__
-#define __APBUART_PCI_H__
-
-#include <apbuart.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Register APBUART driver, if APBUART devices are found.
- * bus = pointer to AMBA bus description used to search for APBUART(s).
- *
- */
-
-int apbuart_pci_register (struct ambapp_bus * bus);
-
-/* This function must be called on APBUART interrupt. Called from the
- * PCI interrupt handler.
- * irq = AMBA IRQ assigned to the APBUART device, is found by reading
- * pending register on IRQMP connected to the APBUART device.
- *
- */
-void apbuartpci_interrupt_handler (int irq, void *arg);
-
-extern void (*apbuart_pci_int_reg) (void *handler, int irq, void *arg);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __APBUART_PCI_H__ */
diff --git a/c/src/lib/libbsp/sparc/shared/include/apbuart_rasta.h b/c/src/lib/libbsp/sparc/shared/include/apbuart_rasta.h
deleted file mode 100644
index d502970..0000000
--- a/c/src/lib/libbsp/sparc/shared/include/apbuart_rasta.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/**
- * @file
- * @ingroup uart
- * @brief APBUART RASTA via PCI - driver interface
- */
-
-/*
- * COPYRIGHT (c) 2007.
- * Gaisler Research
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- *
- */
-
-#ifndef __APBUART_RASTA_H__
-#define __APBUART_RASTA_H__
-
-#include <apbuart.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Register APBUART driver, if APBUART devices are found.
- * bus = pointer to AMBA bus description used to search for APBUART(s).
- *
- */
-
-int apbuart_rasta_register(struct ambapp_bus *bus);
-
-/* This function must be called on APBUART interrupt. Called from the
- * RASTA interrupt handler.
- * irq = AMBA IRQ assigned to the APBUART device, is found by reading
- * pending register on IRQMP connected to the APBUART device.
- *
- */
-void apbuartrasta_interrupt_handler(int irq, void *arg);
-
-extern void (*apbuart_rasta_int_reg)(void *handler, int irq, void *arg);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __APBUART_RASTA_H__ */
diff --git a/c/src/lib/libbsp/sparc/shared/include/b1553brm_pci.h b/c/src/lib/libbsp/sparc/shared/include/b1553brm_pci.h
deleted file mode 100644
index e7ed277..0000000
--- a/c/src/lib/libbsp/sparc/shared/include/b1553brm_pci.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/**
- * @file
- * @ingroup 1553
- * @brief Macros used for brm controller via PCI
- */
-
-/*
- * COPYRIGHT (c) 2006.
- * Gaisler Research
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- *
- */
-
-#ifndef __B1553BRM_PCI_H__
-#define __B1553BRM_PCI_H__
-
-#include <b1553brm.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Register BRM driver
- * See (struct brm_reg).w_ctrl for clksel and clkdiv.
- * See Enhanced register (the least signinficant 2 bits) in BRM Core for brm_freq
- * bus = &ambapp_plb for LEON3. (LEON2 not yet supported for this driver)
- *
- * Memory setup:
- * memarea = 128k aligned pointer to memory (if zero malloc will be used) (as the CPU sees it)
- * hw_address = address that HW must use to access memarea. (used in the translation process)
- */
-
-int b1553brm_pci_register(
- struct ambapp_bus *bus,
- unsigned int clksel,
- unsigned int clkdiv,
- unsigned int brm_freq,
- unsigned int memarea,
- unsigned int hw_address
- );
-
-
-/* This function must be called on BRM interrupt. Called from the
- * PCI interrupt handler. irq = AMBA IRQ MASK assigned to the BRM device,
- * is found by reading pending register on IRQMP connected to BRM
- * device.
- *
- * Return 0=not handled. nono-zero=handled
- */
-int b1553brm_pci_interrupt_handler(int irq, void *arg);
-
-extern void (*b1553brm_pci_int_reg)(void *handler, int irq, void *arg);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __B1553BRM_PCI_H__ */
diff --git a/c/src/lib/libbsp/sparc/shared/include/b1553brm_rasta.h b/c/src/lib/libbsp/sparc/shared/include/b1553brm_rasta.h
deleted file mode 100644
index bc19644..0000000
--- a/c/src/lib/libbsp/sparc/shared/include/b1553brm_rasta.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/**
- * @file
- * @ingroup 1553
- * @brief Macros used for brm RASTA controller
- */
-
-/*
- * COPYRIGHT (c) 2006.
- * Gaisler Research
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- *
- */
-
-#ifndef __B1553BRM_RASTA_H__
-#define __B1553BRM_RASTA_H__
-
-#include <b1553brm.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Register BRM driver
- * See (struct brm_reg).w_ctrl for clksel and clkdiv.
- * See Enhanced register (the least signinficant 2 bits) in BRM Core for brm_freq
- * bus = &ambapp_plb for LEON3. (LEON2 not yet supported for this driver)
- *
- * Memory setup:
- * memarea = 128k aligned pointer to memory (if zero malloc will be used) (as the CPU sees it)
- * hw_address = address that HW must use to access memarea. (used in the translation process)
- */
-
-int b1553brm_rasta_register(
- struct ambapp_bus *bus,
- unsigned int clksel,
- unsigned int clkdiv,
- unsigned int brm_freq,
- unsigned int memarea,
- unsigned int hw_address
-);
-
-
-/* This function must be called on BRM interrupt. Called from the
- * PCI interrupt handler. irq = AMBA IRQ MASK assigned to the BRM device,
- * is found by reading pending register on IRQMP connected to BRM
- * device.
- *
- * Return 0=not handled. nono-zero=handled
- */
-int b1553brm_rasta_interrupt_handler(int irq, void *arg);
-
-extern void (*b1553brm_rasta_int_reg)(void *handler, int irq, void *arg);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __B1553BRM_RASTA_H__ */
diff --git a/c/src/lib/libbsp/sparc/shared/include/gr_701.h b/c/src/lib/libbsp/sparc/shared/include/gr_701.h
new file mode 100644
index 0000000..0ff75cc
--- /dev/null
+++ b/c/src/lib/libbsp/sparc/shared/include/gr_701.h
@@ -0,0 +1,48 @@
+/* GR-701 PCI Target driver.
+ *
+ * COPYRIGHT (c) 2008.
+ * Cobham Gaisler AB.
+ *
+ * Configures the GR-701 interface PCI board.
+ * This driver provides a AMBA PnP bus by using the general part
+ * of the AMBA PnP bus driver (ambapp_bus.c).
+ *
+ * Driver resources for the AMBA PnP bus provided can be set using
+ * gr701_set_resources().
+ *
+ * The license and distribution terms for this file may be
+ * found in found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef __GR_701_H__
+#define __GR_701_H__
+
+#include <drvmgr/drvmgr.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* An array of pointers to GR-701 resources. The resources will be
+ * used by the drivers controlling the cores on the GR-701 target AMBA bus.
+ *
+ * The gr_rasta_io_resources is declared weak so that the user can override the
+ * default configuration.
+ */
+extern struct drvmgr_bus_res *gr701_resources[];
+
+#define GR701_OPTIONS_AMBA 0x01
+#define GR701_OPTIONS_IRQ 0x02
+
+/* Print information about GR-RASTA-IO PCI board */
+void gr701_print(int options);
+
+/* Register GR-701 driver */
+void gr701_register_drv(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/c/src/lib/libbsp/sparc/shared/include/gr_rasta_adcdac.h b/c/src/lib/libbsp/sparc/shared/include/gr_rasta_adcdac.h
new file mode 100644
index 0000000..42c7c56
--- /dev/null
+++ b/c/src/lib/libbsp/sparc/shared/include/gr_rasta_adcdac.h
@@ -0,0 +1,49 @@
+/* GR-RASTA-ADCDAC PCI Target driver.
+ *
+ * COPYRIGHT (c) 2008.
+ * Cobham Gaisler AB.
+ *
+ * Configures the GR-RASTA-ADCDAC interface PCI board.
+ * This driver provides a AMBA PnP bus by using the general part
+ * of the AMBA PnP bus driver (ambapp_bus.c).
+ *
+ * Driver resources for the AMBA PnP bus provided can be set using
+ * gr_rasta_adcdac_set_resources().
+ *
+ * The license and distribution terms for this file may be
+ * found in found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef __GR_RASTA_ADCDAC_H__
+#define __GR_RASTA_ADCDAC_H__
+
+#include <drvmgr/drvmgr.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* An array of pointers to GR-RASTA-ADCDAC resources. The resources will be
+ * used by the drivers controlling the cores on the GR-RASTA-ADCDAC target AMBA bus.
+ *
+ * The gr_rasta_io_resources is declared weak so that the user can override the
+ * default configuration.
+ */
+extern struct drvmgr_bus_res *gr_rasta_adcdac_resources[];
+
+/* Options to gr_rasta_io_print function */
+#define RASTA_ADCDAC_OPTIONS_AMBA 0x01 /* Print AMBA bus devices */
+#define RASTA_ADCDAC_OPTIONS_IRQ 0x02 /* Print current IRQ setup */
+
+/* Print information about GR-RASTA-IO PCI board */
+void gr_rasta_adcdac_print(int options);
+
+/* Register GR-RASTA-IO driver */
+void gr_rasta_adcdac_register_drv(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/c/src/lib/libbsp/sparc/shared/include/gr_rasta_io.h b/c/src/lib/libbsp/sparc/shared/include/gr_rasta_io.h
new file mode 100644
index 0000000..0aea86d
--- /dev/null
+++ b/c/src/lib/libbsp/sparc/shared/include/gr_rasta_io.h
@@ -0,0 +1,49 @@
+/* GR-RASTA-IO PCI Target driver.
+ *
+ * COPYRIGHT (c) 2008.
+ * Cobham Gaisler AB.
+ *
+ * Configures the GR-RASTA-IO interface PCI board.
+ * This driver provides a AMBA PnP bus by using the general part
+ * of the AMBA PnP bus driver (ambapp_bus.c).
+ *
+ * Driver resources for the AMBA PnP bus provided can be set using
+ * gr_rasta_io_set_resources().
+ *
+ * The license and distribution terms for this file may be
+ * found in found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef __GR_RASTA_IO_H__
+#define __GR_RASTA_IO_H__
+
+#include <drvmgr/drvmgr.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* An array of pointers to GR-RASTA-IO resources. The resources will be
+ * used by the drivers controlling the cores on the GR-RASTA-IO target AMBA bus.
+ *
+ * The gr_rasta_io_resources is declared weak so that the user can override the
+ * default configuration.
+ */
+extern struct drvmgr_bus_res *gr_rasta_io_resources[];
+
+/* Options to gr_rasta_io_print function */
+#define RASTA_IO_OPTIONS_AMBA 0x01 /* Print AMBA bus devices */
+#define RASTA_IO_OPTIONS_IRQ 0x02 /* Print current IRQ setup */
+
+/* Print information about GR-RASTA-IO PCI board */
+void gr_rasta_io_print(int options);
+
+/* Register GR-RASTA-IO driver */
+void gr_rasta_io_register_drv(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/c/src/lib/libbsp/sparc/shared/include/gr_rasta_tmtc.h b/c/src/lib/libbsp/sparc/shared/include/gr_rasta_tmtc.h
new file mode 100644
index 0000000..28b6ea0
--- /dev/null
+++ b/c/src/lib/libbsp/sparc/shared/include/gr_rasta_tmtc.h
@@ -0,0 +1,99 @@
+/* GR-RASTA-TMTC PCI Target driver.
+ *
+ * COPYRIGHT (c) 2008.
+ * Cobham Gaisler AB.
+ *
+ * Configures the GR-RASTA-TMTC interface PCI board.
+ * This driver provides a AMBA PnP bus by using the general part
+ * of the AMBA PnP bus driver (ambapp_bus.c).
+ *
+ * Driver resources for the AMBA PnP bus provided can be set using
+ * gr_rasta_tmtc_set_resources().
+ *
+ * The license and distribution terms for this file may be
+ * found in found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef __GR_RASTA_TMTC_H__
+#define __GR_RASTA_TMTC_H__
+
+#include <drvmgr/drvmgr.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* GPIO TM/TC configuration pin definitions
+ * --31 PWRX (1=PW2APB, 0=TM VC3/4)
+ * --30 PWTC (1=APB2PW, 0=TC MAP1/2)
+ * --29 Redundant TM (1=enable, 0=disable)
+ * --28 Redundant TC (1=enable, 0=disable)
+ * --27 Select TM output (1=GRTM, 0=PTME)
+ * --26 Loop back PW (1=enable, 0=disable)
+ * --25 Transponder clock (1=PLL, 0=PLL bypass)
+ * --24 PWTX-SELECT (0=TX0-0, 1=TX0-1)
+ * --23 PDEC Map Switch (1=on, 0=off)
+ * --22 PDEC Ext CPDU (1=on, 0=off)
+ * --21 PDEC Super User (1=on, 0=off)
+ * --20 PDEC RM On (1=on, 0=off)
+ * --19 PDEC AU Enable (1=on, 0=off)
+ * --18 PDEC Dynamic Mode (1=on, 0=off)
+ * --17 PDEC Priority (1=on, 0=off)
+ * --16 TC PSS Support (1=on, 0=off)
+ * --15 TC Mark (1=on, 0=off)
+ * --14 TC Pseudo (1=on, 0=off)
+ * --13 TC Rising Clock (1=rise, 0=fall)
+ * --12 TC Active High (1=high, 0=low)
+ * --11 Bit Lock Positive (1=high, 0=low)
+ * --10 RF Avail Positive (1=high, 0=low)
+ * -- 9 : 0 SpaceCraft ID
+ */
+
+#define GR_TMTC_GPIO_PWRX (1<<31)
+#define GR_TMTC_GPIO_PWTC (1<<30)
+#define GR_TMTC_GPIO_RED_TM (1<<29)
+#define GR_TMTC_GPIO_RED_TC (1<<28)
+#define GR_TMTC_GPIO_GRTM_SEL (1<<27)
+#define GR_TMTC_GPIO_LB_PW (1<<26)
+#define GR_TMTC_GPIO_TRANSP_CLK (1<<25)
+#define GR_TMTC_GPIO_PWTX_SEL (1<<24)
+#define GR_TMTC_GPIO_PDEC_MAP (1<<23)
+#define GR_TMTC_GPIO_PDEC_CPDU (1<<22)
+#define GR_TMTC_GPIO_PDEC_SU (1<<21)
+#define GR_TMTC_GPIO_PDEC_RM (1<<20)
+#define GR_TMTC_GPIO_PDEC_AU (1<<19)
+#define GR_TMTC_GPIO_PDEC_DYN_MODE (1<<18)
+#define GR_TMTC_GPIO_PDEC_PRIO (1<<17)
+#define GR_TMTC_GPIO_TC_PSS (1<<16)
+#define GR_TMTC_GPIO_TC_MARK (1<<15)
+#define GR_TMTC_GPIO_TC_PSEUDO (1<<14)
+#define GR_TMTC_GPIO_TC_RISING_CLK (1<<13)
+#define GR_TMTC_GPIO_TC_ACTIVE_HIGH (1<<12)
+#define GR_TMTC_GPIO_TC_BIT_LOCK (1<<11)
+#define GR_TMTC_GPIO_TC_RF_AVAIL (1<<10)
+#define GR_TMTC_GPIO_SCID (0x000003ff)
+
+/* An array of pointers to GR-RASTA-TMTC bus resources. The resources will be
+ * used by the device drivers controlling the cores on the GR-RASTA-IO target
+ * AMBA bus.
+ *
+ * The array is defined weak, and defualts to no resources.
+ */
+extern struct drvmgr_bus_res *gr_rasta_tmtc_resources[];
+
+/* Options to gr_rasta_io_print function */
+#define RASTA_TMTC_OPTIONS_AMBA 0x01 /* Print AMBA bus devices */
+#define RASTA_TMTC_OPTIONS_IRQ 0x02 /* Print current IRQ setup */
+
+/* Print information about GR-RASTA-TMTC PCI board */
+void gr_rasta_tmtc_print(int options);
+
+/* Register GR-RASTA-TMTC driver */
+void gr_rasta_tmtc_register_drv(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/c/src/lib/libbsp/sparc/shared/include/gr_tmtc_1553.h b/c/src/lib/libbsp/sparc/shared/include/gr_tmtc_1553.h
new file mode 100644
index 0000000..4df89f7
--- /dev/null
+++ b/c/src/lib/libbsp/sparc/shared/include/gr_tmtc_1553.h
@@ -0,0 +1,49 @@
+/* GR-TMTC-1553 PCI Target driver.
+ *
+ * COPYRIGHT (c) 2010.
+ * Cobham Gaisler AB.
+ *
+ * Configures the GR-TMTC-1553 interface PCI board.
+ * This driver provides a AMBA PnP bus by using the general part
+ * of the AMBA PnP bus driver (ambapp_bus.c).
+ *
+ * Driver resources for the AMBA PnP bus provided can be set using
+ * gr_tmtc_1553_set_resources().
+ *
+ * The license and distribution terms for this file may be
+ * found in found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef __GR_TMTC_1553_H__
+#define __GR_TMTC_1553_H__
+
+#include <drvmgr/drvmgr.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* An array of pointers to GR-TMTC-1553 resources. The resources will be
+ * used by the drivers controlling the cores on the GR-TMTC-1553 target AMBA bus.
+ *
+ * The gr_rasta_io_resources is declared weak so that the user can override the
+ * default configuration.
+ */
+extern struct drvmgr_bus_res *gr_tmtc_1553_resources[];
+
+/* Options to gr_rasta_io_print function */
+#define TMTC_1553_OPTIONS_AMBA 0x01 /* Print AMBA bus devices */
+#define TMTC_1553_OPTIONS_IRQ 0x02 /* Print current IRQ setup */
+
+/* Print information about GR-RASTA-IO PCI board */
+void gr_tmtc_1553_print(int options);
+
+/* Register GR-RASTA-IO driver */
+void gr_tmtc_1553_register_drv(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/c/src/lib/libbsp/sparc/shared/include/grcan_rasta.h b/c/src/lib/libbsp/sparc/shared/include/grcan_rasta.h
deleted file mode 100644
index dd5ef95..0000000
--- a/c/src/lib/libbsp/sparc/shared/include/grcan_rasta.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/**
- * @file
- * @ingroup can
- * @brief Registers the GRCAN for RASTA
- */
-
-#ifndef __GRCAN_RASTA_H__
-#define __GRCAN_RASTA_H__
-
-#include <grcan.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Registers the GRCAN for RASTA
- *
- * rambase is address of the first GRCAN core has it's TX buffer, followed by
- * it's RX buffer
- */
-int grcan_rasta_ram_register(struct ambapp_bus *abus, int rambase);
-
-extern void (*grcan_rasta_int_reg)(void *handler, int irq, void *arg);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/c/src/lib/libbsp/sparc/shared/include/grspw_pci.h b/c/src/lib/libbsp/sparc/shared/include/grspw_pci.h
deleted file mode 100644
index 0e1c6f9..0000000
--- a/c/src/lib/libbsp/sparc/shared/include/grspw_pci.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/**
- * @file
- * @ingroup spw
- * @brief Macros used for GRSPW controller via PCI
- */
-
-/*
- * COPYRIGHT (c) 2006.
- * Gaisler Research
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- *
- */
-
-#ifndef __GRSPW_PCI_H__
-#define __GRSPW_PCI_H__
-
-#include <grspw.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Register GRSPW Driver
- * bus = &ambapp_plb for LEON3
- *
- * Memory setup:
- * memarea = 128k aligned pointer to memory (if zero malloc will be used) (as the CPU sees it)
- * hw_address = address that HW must use to access memarea. (used in the translation process)
- */
-
-int grspw_pci_register (struct ambapp_bus *bus,
- unsigned int memarea, unsigned int hw_address);
-
-
-/* This function must be called on BRM interrupt. Called from the
- * PCI interrupt handler. irq = AMBA IRQ MASK assigned to the BRM device,
- * is found by reading pending register on IRQMP connected to BRM
- * device.
- *
- * Return 0=not handled. nono-zero=handled
- */
-unsigned int grspw_pci_interrupt_handler (int irq, void *arg);
-
-extern void (*grspw_pci_int_reg) (void *handler, int irq, void *arg);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __GRSPW_PCI_H__ */
diff --git a/c/src/lib/libbsp/sparc/shared/include/grspw_rasta.h b/c/src/lib/libbsp/sparc/shared/include/grspw_rasta.h
deleted file mode 100644
index 1d33603..0000000
--- a/c/src/lib/libbsp/sparc/shared/include/grspw_rasta.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/**
- * @file
- * @ingroup spw
- * @brief Macros used for RASTA PCI GRSPW controller
- */
-
-/*
- * COPYRIGHT (c) 2006.
- * Gaisler Research
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- *
- */
-
-#ifndef __GRSPW_RASTA_H__
-#define __GRSPW_RASTA_H__
-
-#include <grspw.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Register GRSPW Driver
- * bus = &ambapp_plb for LEON3
- *
- * Memory setup:
- * ram_base = 128k aligned pointer to memory (as the CPU sees it)
- */
-
-int grspw_rasta_register(
- struct ambapp_bus *bus,
- unsigned int ram_base
- );
-
-/* This function must be called on GRSPW interrupt. Called from the
- * PCI interrupt handler. irq = AMBA IRQ MASK assigned to the GRSPW device,
- * is found by reading pending register on IRQMP connected to GRSPW
- * device.
- *
- */
-void grspw_rasta_interrupt_handler(unsigned int status);
-
-/* callback to register interrupt handler */
-extern void (*grspw_rasta_int_reg)(void *handler, int irq, void *arg);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __GRSPW_RASTA_PCI_H__ */
diff --git a/c/src/lib/libbsp/sparc/shared/include/occan_pci.h b/c/src/lib/libbsp/sparc/shared/include/occan_pci.h
deleted file mode 100644
index d3c6d1b..0000000
--- a/c/src/lib/libbsp/sparc/shared/include/occan_pci.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/**
- * @file
- * @ingroup can
- * @brief OC_CAN controller via PCI - driver interface
- */
-
-/*
- * COPYRIGHT (c) 2007.
- * Gaisler Research
- *
- * The license and distribution terms for this file may be
- * found in the file LICENSE in this distribution or at
- * http://www.rtems.org/license/LICENSE.
- *
- */
-
-#ifndef __OCCAN_PCI_H__
-#define __OCCAN_PCI_H__
-
-#include <occan.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Register OC_CAN driver
- * bus = pointer to AMBA bus description used to search for OC_CAN contrller(s).
- */
-
-int occan_pci_register(struct ambapp_bus *bus);
-
-/* This function must be called on OC_CAN interrupt. Called from the
- * PCI interrupt handler. irq = AMBA IRQ assigned to the OC_CAN device,
- * is found by reading pending register on IRQMP connected to the OC_CAN
- * device.
- *
- */
-void occanpci_interrupt_handler(int irq, void *arg);
-
-extern void (*occan_pci_int_reg)(void *handler, int irq, void *arg);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __OCCAN_PCI_H__ */
diff --git a/c/src/lib/libbsp/sparc/shared/pci/gr_701.c b/c/src/lib/libbsp/sparc/shared/pci/gr_701.c
new file mode 100644
index 0000000..1483008
--- /dev/null
+++ b/c/src/lib/libbsp/sparc/shared/pci/gr_701.c
@@ -0,0 +1,592 @@
+/* GR-701 PCI Target driver.
+ *
+ * COPYRIGHT (c) 2008.
+ * Cobham Gaisler AB.
+ *
+ * Configures the GR-701 interface PCI board.
+ * This driver provides a AMBA PnP bus by using the general part
+ * of the AMBA PnP bus driver (ambapp_bus.c).
+ *
+ * Driver resources for the AMBA PnP bus provided can be set using
+ * gr701_set_resources().
+ *
+ * The license and distribution terms for this file may be
+ * found in found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+
+#include <bsp.h>
+#include <rtems/bspIo.h>
+#include <pci.h>
+#include <pci/access.h>
+
+#include <ambapp.h>
+
+#include <ambapp.h>
+#include <drvmgr/drvmgr.h>
+#include <drvmgr/ambapp_bus.h>
+#include <drvmgr/pci_bus.h>
+#include <genirq.h>
+
+#include <gr_701.h>
+
+/* Offset from 0x80000000 (dual bus version) */
+#define AHB1_BASE_ADDR 0x80000000
+#define AHB1_IOAREA_BASE_ADDR 0x80100000
+
+/* #define DEBUG 1 */
+
+#ifdef DEBUG
+#define DBG(x...) printk(x)
+#else
+#define DBG(x...)
+#endif
+
+int gr701_init1(struct drvmgr_dev *dev);
+int gr701_init2(struct drvmgr_dev *dev);
+
+#define READ_REG(address) (*(volatile unsigned int *)address)
+
+/* PCI bride reg layout on AMBA side */
+struct amba_bridge_regs {
+ volatile unsigned int bar0;
+ volatile unsigned int bar1;
+ volatile unsigned int bar2;
+ volatile unsigned int bar3;
+ volatile unsigned int bar4;/* 0x10 */
+
+ volatile unsigned int unused[4*3-1];
+
+ volatile unsigned int ambabars[1]; /* 0x40 */
+};
+
+/* PCI bride reg layout on PCI side */
+struct pci_bridge_regs {
+ volatile unsigned int bar0;
+ volatile unsigned int bar1;
+ volatile unsigned int bar2;
+ volatile unsigned int bar3;
+ volatile unsigned int bar4; /* 0x10 */
+
+ volatile unsigned int ilevel;
+ volatile unsigned int ipend;
+ volatile unsigned int iforce;
+ volatile unsigned int istatus;
+ volatile unsigned int iclear;
+ volatile unsigned int imask;
+};
+
+/* Private data structure for driver */
+struct gr701_priv {
+ /* Driver management */
+ struct drvmgr_dev *dev;
+ char prefix[16];
+
+ struct pci_bridge_regs *pcib;
+ struct amba_bridge_regs *ambab;
+
+ /* PCI */
+ pci_dev_t pcidev;
+ struct pci_dev_info *devinfo;
+
+ /* IRQ */
+ genirq_t genirq;
+ int interrupt_cnt;
+
+ /* GR-701 Address translation */
+ struct drvmgr_map_entry bus_maps_up[2];
+ struct drvmgr_map_entry bus_maps_down[2];
+
+ /* AMBA Plug&Play information on GR-701 */
+ struct ambapp_bus abus;
+ struct ambapp_mmap amba_maps[3];
+ struct ambapp_config config;
+};
+
+int ambapp_gr701_int_register(
+ struct drvmgr_dev *dev,
+ int irq,
+ const char *info,
+ drvmgr_isr handler,
+ void *arg);
+int ambapp_gr701_int_unregister(
+ struct drvmgr_dev *dev,
+ int irq,
+ drvmgr_isr isr,
+ void *arg);
+int ambapp_gr701_int_unmask(
+ struct drvmgr_dev *dev,
+ int irq);
+int ambapp_gr701_int_mask(
+ struct drvmgr_dev *dev,
+ int irq);
+int ambapp_gr701_int_clear(
+ struct drvmgr_dev *dev,
+ int irq);
+int ambapp_gr701_get_params(
+ struct drvmgr_dev *dev,
+ struct drvmgr_bus_params *params);
+
+struct ambapp_ops ambapp_gr701_ops = {
+ .int_register = ambapp_gr701_int_register,
+ .int_unregister = ambapp_gr701_int_unregister,
+ .int_unmask = ambapp_gr701_int_unmask,
+ .int_mask = ambapp_gr701_int_mask,
+ .int_clear = ambapp_gr701_int_clear,
+ .get_params = ambapp_gr701_get_params
+};
+
+struct drvmgr_drv_ops gr701_ops =
+{
+ .init = {gr701_init1, gr701_init2, NULL, NULL},
+ .remove = NULL,
+ .info = NULL
+};
+
+struct pci_dev_id_match gr701_ids[] =
+{
+ PCIID_DEVVEND(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_701),
+ PCIID_END_TABLE /* Mark end of table */
+};
+
+struct pci_drv_info gr701_info =
+{
+ {
+ DRVMGR_OBJ_DRV, /* Driver */
+ NULL, /* Next driver */
+ NULL, /* Device list */
+ DRIVER_PCI_GAISLER_GR701_ID, /* Driver ID */
+ "GR-701_DRV", /* Driver Name */
+ DRVMGR_BUS_TYPE_PCI, /* Bus Type */
+ &gr701_ops,
+ NULL, /* Funcs */
+ 0, /* No devices yet */
+ 0,
+ },
+ &gr701_ids[0]
+};
+
+/* Driver resources configuration for the AMBA bus on the GR-701 board.
+ * It is declared weak so that the user may override it from the project file,
+ * if the default settings are not enough.
+ *
+ * The configuration consists of an array of configuration pointers, each
+ * pointer determine the configuration of one GR-701 board. Pointer
+ * zero is for board0, pointer 1 for board1 and so on.
+ *
+ * The array must end with a NULL pointer.
+ */
+struct drvmgr_bus_res *gr701_resources[] __attribute__((weak)) =
+{
+ NULL
+};
+int gr701_resources_cnt = 0;
+
+void gr701_register_drv(void)
+{
+ DBG("Registering GR-701 PCI driver\n");
+ drvmgr_drv_register(&gr701_info.general);
+}
+
+void gr701_interrupt(void *arg)
+{
+ struct gr701_priv *priv = arg;
+ unsigned int status;
+ int irq = 0;
+
+ while ( (status=priv->pcib->istatus) != 0 ) {
+ priv->interrupt_cnt++; /* An interrupt was generated */
+ irq = status;
+ genirq_doirq(priv->genirq, irq);
+ /* ACK interrupt */
+ priv->pcib->istatus = 0;
+ }
+
+ /* ACK interrupt, this is because PCI is Level, so the IRQ Controller still drives the IRQ. */
+ if ( irq )
+ drvmgr_interrupt_clear(priv->dev, 0);
+}
+
+int gr701_hw_init(struct gr701_priv *priv)
+{
+ uint32_t com1;
+ struct pci_bridge_regs *pcib;
+ struct amba_bridge_regs *ambab;
+ int mst;
+ unsigned int pci_freq_hz;
+ pci_dev_t pcidev = priv->pcidev;
+ struct pci_dev_info *devinfo = priv->devinfo;
+
+ /* Set up PCI ==> AMBA */
+ priv->pcib = pcib = (void *)devinfo->resources[0].address;
+ pcib->bar0 = 0xfc000000;
+
+ /* Set up GR701 AMBA Masters connection to PCI */
+ priv->ambab = ambab = (struct amba_bridge_regs *)(
+ devinfo->resources[1].address + 0x400);
+
+ /* Init all msters, max 16 */
+ for (mst=0; mst<16; mst++) {
+ ambab->ambabars[mst] = 0x40000000;
+ if (READ_REG(&ambab->ambabars[mst]) != 0x40000000)
+ break;
+ }
+
+ /* Setup Address translation for AMBA bus, assume that PCI BAR
+ * are mapped 1:1 to CPU.
+ */
+
+ priv->amba_maps[0].size = 0x04000000;
+ priv->amba_maps[0].local_adr = devinfo->resources[1].address;
+ priv->amba_maps[0].remote_adr = 0xfc000000;
+
+ /* Mark end of table */
+ priv->amba_maps[1].size=0;
+ priv->amba_maps[1].local_adr = 0;
+ priv->amba_maps[1].remote_adr = 0;
+
+ /* Setup DOWN-streams address translation */
+ priv->bus_maps_down[0].name = "PCI BAR1 -> AMBA";
+ priv->bus_maps_down[0].size = priv->amba_maps[0].size;
+ priv->bus_maps_down[0].from_adr = (void *)devinfo->resources[1].address;
+ priv->bus_maps_down[0].to_adr = (void *)0xfc000000;
+
+ /* Setup UP-streams address translation */
+ priv->bus_maps_up[0].name = "AMBA PCIF Window";
+ priv->bus_maps_up[0].size = 0x10000000;
+ priv->bus_maps_up[0].from_adr = (void *)0xe0000000;
+ priv->bus_maps_up[0].to_adr = (void *)0x40000000;
+
+ /* Mark end of translation tables */
+ priv->bus_maps_down[1].size = 0;
+ priv->bus_maps_up[1].size = 0;
+
+ /* Enable I/O and Mem accesses */
+ pci_cfg_r32(pcidev, PCI_COMMAND, &com1);
+ com1 |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
+ pci_cfg_w32(pcidev, PCI_COMMAND, com1);
+
+ /* Start AMBA PnP scan at first AHB bus */
+ ambapp_scan(&priv->abus, devinfo->resources[1].address + 0x3f00000,
+ NULL, &priv->amba_maps[0]);
+
+ /* Frequency is the same as the PCI bus frequency */
+ drvmgr_freq_get(priv->dev, NULL, &pci_freq_hz);
+
+ /* Initialize Frequency of AMBA bus */
+ ambapp_freq_init(&priv->abus, NULL, pci_freq_hz);
+
+ /* Init IRQ controller (avoid IRQ generation) */
+ pcib->imask = 0x0000;
+ pcib->ipend = 0;
+ pcib->iclear = 0xffff;
+ pcib->iforce = 0;
+ pcib->ilevel = 0x0;
+
+ /* Successfully registered the GR-701 board */
+ return 0;
+}
+
+void gr701_hw_init2(struct gr701_priv *priv)
+{
+ /* Enable PCI Master (for DMA) */
+ pci_master_enable(priv->pcidev);
+}
+
+/* Called when a PCI target is found with the PCI device and vendor ID
+ * given in gr701_ids[].
+ */
+int gr701_init1(struct drvmgr_dev *dev)
+{
+ struct gr701_priv *priv;
+ struct pci_dev_info *devinfo;
+ uint32_t bar0, bar1, bar0_size, bar1_size;
+
+ priv = malloc(sizeof(struct gr701_priv));
+ if ( !priv )
+ return DRVMGR_NOMEM;
+
+ memset(priv, 0, sizeof(*priv));
+ dev->priv = priv;
+ priv->dev = dev;
+
+ /* Determine number of configurations */
+ if ( gr701_resources_cnt == 0 ) {
+ while ( gr701_resources[gr701_resources_cnt] )
+ gr701_resources_cnt++;
+ }
+
+ /* Generate Device prefix */
+
+ strcpy(priv->prefix, "/dev/gr701_0");
+ priv->prefix[11] += dev->minor_drv;
+ mkdir(priv->prefix, S_IRWXU | S_IRWXG | S_IRWXO);
+ priv->prefix[12] = '/';
+ priv->prefix[13] = '\0';
+
+ priv->devinfo = devinfo = (struct pci_dev_info *)dev->businfo;
+ priv->pcidev = devinfo->pcidev;
+ bar0 = devinfo->resources[0].address;
+ bar0_size = devinfo->resources[0].size;
+ bar1 = devinfo->resources[1].address;
+ bar1_size = devinfo->resources[1].size;
+ printf("\n\n--- GR-701[%d] ---\n", dev->minor_drv);
+ printf(" PCI BUS: 0x%x, SLOT: 0x%x, FUNCTION: 0x%x\n",
+ PCI_DEV_EXPAND(priv->pcidev));
+ printf(" PCI VENDOR: 0x%04x, DEVICE: 0x%04x\n\n\n",
+ devinfo->id.vendor, devinfo->id.device);
+ printf(" PCI BAR[0]: 0x%lx - 0x%lx\n", bar0, bar0 + bar0_size - 1);
+ printf(" PCI BAR[1]: 0x%lx - 0x%lx\n", bar1, bar1 + bar1_size - 1);
+ printf(" IRQ: %d\n\n\n", devinfo->irq);
+
+ /* all neccessary space assigned to GR-701 target? */
+ if ((bar0_size == 0) || (bar1_size == 0))
+ return DRVMGR_ENORES;
+
+ priv->genirq = genirq_init(16);
+ if ( priv->genirq == NULL ) {
+ free(priv);
+ dev->priv = NULL;
+ return DRVMGR_FAIL;
+ }
+
+ if ( gr701_hw_init(priv) ) {
+ genirq_destroy(priv->genirq);
+ free(priv);
+ dev->priv = NULL;
+ printf(" Failed to initialize GR-701 HW\n");
+ return DRVMGR_FAIL;
+ }
+
+ /* Init amba bus */
+ priv->config.abus = &priv->abus;
+ priv->config.ops = &ambapp_gr701_ops;
+ priv->config.maps_up = &priv->bus_maps_up[0];
+ priv->config.maps_down = &priv->bus_maps_down[0];
+ if ( priv->dev->minor_drv < gr701_resources_cnt ) {
+ priv->config.resources = gr701_resources[priv->dev->minor_drv];
+ } else {
+ priv->config.resources = NULL;
+ }
+
+ /* Create and register AMBA PnP bus. */
+ return ambapp_bus_register(dev, &priv->config);
+}
+
+/* Called when a PCI target is found with the PCI device and vendor ID
+ * given in gr701_ids[].
+ */
+int gr701_init2(struct drvmgr_dev *dev)
+{
+ struct gr701_priv *priv = dev->priv;
+
+ /* Clear any old interrupt requests */
+ drvmgr_interrupt_clear(dev, 0);
+
+ /* Enable System IRQ so that GR-701 PCI target interrupt goes through.
+ *
+ * It is important to enable it in stage init2. If interrupts were
+ * enabled in init1 this might hang the system when more than one PCI
+ * board is connected, this is because PCI interrupts might be shared
+ * and PCI target 2 have not initialized and might therefore drive
+ * interrupt already when entering init1().
+ */
+ drvmgr_interrupt_register(dev, 0, "gr701", gr701_interrupt, priv);
+
+ gr701_hw_init2(priv);
+
+ return DRVMGR_OK;
+}
+
+int ambapp_gr701_int_register(
+ struct drvmgr_dev *dev,
+ int irq,
+ const char *info,
+ drvmgr_isr handler,
+ void *arg)
+{
+ struct gr701_priv *priv = dev->parent->dev->priv;
+ rtems_interrupt_level level;
+ int status;
+
+ rtems_interrupt_disable(level);
+
+ status = genirq_register(priv->genirq, irq, handler, arg);
+ if ( status == 0 ) {
+ /* Clear IRQ for first registered handler */
+ priv->pcib->iclear = (1<<irq);
+ } else if ( status == 1 )
+ status = 0;
+
+ if (status != 0) {
+ rtems_interrupt_enable(level);
+ return DRVMGR_FAIL;
+ }
+
+ status = genirq_enable(priv->genirq, irq, handler, arg);
+ if ( status == 0 ) {
+ /* Enable IRQ for first enabled handler only */
+ priv->pcib->imask |= (1<<irq); /* unmask interrupt source */
+ } else if ( status == 1 )
+ status = DRVMGR_OK;
+
+ rtems_interrupt_enable(level);
+
+ return status;
+}
+
+int ambapp_gr701_int_unregister(
+ struct drvmgr_dev *dev,
+ int irq,
+ drvmgr_isr isr,
+ void *arg)
+{
+ struct gr701_priv *priv = dev->parent->dev->priv;
+ rtems_interrupt_level level;
+ int status;
+
+ rtems_interrupt_disable(level);
+
+ status = genirq_disable(priv->genirq, irq, isr, arg);
+ if ( status == 0 ) {
+ /* Disable IRQ only when no enabled handler exists */
+ priv->pcib->imask &= ~(1<<irq); /* mask interrupt source */
+ }
+
+ status = genirq_unregister(priv->genirq, irq, isr, arg);
+ if ( status != 0 )
+ status = DRVMGR_FAIL;
+
+ rtems_interrupt_enable(level);
+
+ return status;
+}
+
+int ambapp_gr701_int_unmask(
+ struct drvmgr_dev *dev,
+ int irq)
+{
+ struct gr701_priv *priv = dev->parent->dev->priv;
+ rtems_interrupt_level level;
+
+ DBG("GR-701 IRQ %d: enable\n", irq);
+
+ if ( genirq_check(priv->genirq, irq) )
+ return DRVMGR_FAIL;
+
+ rtems_interrupt_disable(level);
+
+ /* Enable IRQ */
+ priv->pcib->imask |= (1<<irq); /* unmask interrupt source */
+
+ rtems_interrupt_enable(level);
+
+ return DRVMGR_OK;
+}
+
+int ambapp_gr701_int_mask(
+ struct drvmgr_dev *dev,
+ int irq)
+{
+ struct gr701_priv *priv = dev->parent->dev->priv;
+ rtems_interrupt_level level;
+
+ DBG("GR-701 IRQ %d: disable\n", irq);
+
+ if ( genirq_check(priv->genirq, irq) )
+ return DRVMGR_FAIL;
+
+ rtems_interrupt_disable(level);
+
+ /* Disable IRQ */
+ priv->pcib->imask &= ~(1<<irq); /* mask interrupt source */
+
+ rtems_interrupt_enable(level);
+
+ return DRVMGR_OK;
+}
+
+int ambapp_gr701_int_clear(
+ struct drvmgr_dev *dev,
+ int irq)
+{
+ struct gr701_priv *priv = dev->parent->dev->priv;
+
+ if ( genirq_check(priv->genirq, irq) )
+ return DRVMGR_FAIL;
+
+ priv->pcib->iclear = (1<<irq);
+
+ return DRVMGR_OK;
+}
+
+int ambapp_gr701_get_params(struct drvmgr_dev *dev, struct drvmgr_bus_params *params)
+{
+ struct gr701_priv *priv = dev->parent->dev->priv;
+
+ /* Device name prefix pointer, skip /dev */
+ params->dev_prefix = &priv->prefix[5];
+
+ return 0;
+}
+
+void gr701_print_dev(struct drvmgr_dev *dev, int options)
+{
+ struct gr701_priv *priv = dev->priv;
+ struct pci_dev_info *devinfo = priv->devinfo;
+ unsigned int freq_hz;
+ uint32_t bar0, bar1, bar0_size, bar1_size;
+
+ /* Print */
+ printf("--- GR-701 [bus 0x%x, dev 0x%x, fun 0x%x] ---\n",
+ PCI_DEV_EXPAND(priv->pcidev));
+ bar0 = devinfo->resources[0].address;
+ bar0_size = devinfo->resources[0].size;
+ bar1 = devinfo->resources[1].address;
+ bar1_size = devinfo->resources[1].size;
+
+ printf(" PCI BAR[0]: 0x%lx - 0x%lx\n", bar0, bar0 + bar0_size - 1);
+ printf(" PCI BAR[1]: 0x%lx - 0x%lx\n", bar1, bar1 + bar1_size - 1);
+ printf(" IRQ: %d\n", devinfo->irq);
+
+ /* Frequency is the same as the PCI bus frequency */
+ drvmgr_freq_get(dev, 0, &freq_hz);
+
+ printf(" FREQ: %u Hz\n", freq_hz);
+ printf(" IMASK: 0x%08x\n", priv->pcib->imask);
+ printf(" IPEND: 0x%08x\n", priv->pcib->ipend);
+
+ /* Print amba config */
+ if ( options & GR701_OPTIONS_AMBA ) {
+ ambapp_print(&priv->abus, 10);
+ }
+
+#if 0
+ /* Print IRQ handlers and their arguments */
+ if ( options & GR701_OPTIONS_IRQ ) {
+ int i;
+ for(i=0; i<16; i++) {
+ printf(" IRQ[%02d]: 0x%x, arg: 0x%x\n",
+ i, (unsigned int)priv->isrs[i].handler, (unsigned int)priv->isrs[i].arg);
+ }
+ }
+#endif
+}
+
+void gr701_print(int options)
+{
+ struct pci_drv_info *drv = &gr701_info;
+ struct drvmgr_dev *dev;
+
+ dev = drv->general.dev;
+ while(dev) {
+ gr701_print_dev(dev, options);
+ dev = dev->next_in_drv;
+ }
+}
diff --git a/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_adcdac.c b/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_adcdac.c
new file mode 100644
index 0000000..21ca52c
--- /dev/null
+++ b/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_adcdac.c
@@ -0,0 +1,661 @@
+/* GR-RASTA-ADCDAC PCI Target driver.
+ *
+ * COPYRIGHT (c) 2008.
+ * Cobham Gaisler AB.
+ *
+ * Configures the GR-RASTA-ADCDAC interface PCI board.
+ * This driver provides a AMBA PnP bus by using the general part
+ * of the AMBA PnP bus driver (ambapp_bus.c).
+ *
+ * Driver resources for the AMBA PnP bus provided can be set using
+ * gr_rasta_adcdac_set_resources().
+ *
+ * The license and distribution terms for this file may be
+ * found in found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+
+#include <bsp.h>
+#include <rtems/bspIo.h>
+#include <pci.h>
+
+#include <ambapp.h>
+#include <grlib.h>
+#include <drvmgr/drvmgr.h>
+#include <drvmgr/ambapp_bus.h>
+#include <drvmgr/pci_bus.h>
+#include <genirq.h>
+
+#include <gr_rasta_adcdac.h>
+
+/*#define DEBUG 1*/
+
+#ifdef DEBUG
+#define DBG(x...) printk(x)
+#else
+#define DBG(x...)
+#endif
+
+/* Determines which PCI address the AHB masters will access, it should be
+ * set so that the masters can access the CPU RAM. Default is base of CPU RAM,
+ * CPU RAM is mapped 1:1 to PCI space.
+ */
+extern unsigned int _RAM_START;
+#define AHBMST2PCIADR (((unsigned int)&_RAM_START) & 0xf0000000)
+
+/* PCI ID */
+#define PCIID_VENDOR_GAISLER 0x1AC8
+#define PCIID_DEVICE_GR_RASTA_ADCDAC 0x0014
+
+int gr_rasta_adcdac_init1(struct drvmgr_dev *dev);
+int gr_rasta_adcdac_init2(struct drvmgr_dev *dev);
+
+struct grpci_regs {
+ volatile unsigned int cfg_stat;
+ volatile unsigned int bar0;
+ volatile unsigned int page0;
+ volatile unsigned int bar1;
+ volatile unsigned int page1;
+ volatile unsigned int iomap;
+ volatile unsigned int stat_cmd;
+};
+
+struct gr_rasta_adcdac_ver {
+ const unsigned int amba_freq_hz; /* The frequency */
+ const unsigned int amba_ioarea; /* The address where the PnP IOAREA starts at */
+};
+
+/* Private data structure for driver */
+struct gr_rasta_adcdac_priv {
+ /* Driver management */
+ struct drvmgr_dev *dev;
+ char prefix[20];
+
+ /* PCI */
+ pci_dev_t pcidev;
+ struct pci_dev_info *devinfo;
+ uint32_t ahbmst2pci_map;
+
+ /* IRQ */
+ genirq_t genirq;
+
+ /* GR-RASTA-ADCDAC */
+ struct gr_rasta_adcdac_ver *version;
+ struct irqmp_regs *irq;
+ struct grpci_regs *grpci;
+ struct drvmgr_map_entry bus_maps_down[3];
+ struct drvmgr_map_entry bus_maps_up[2];
+
+ /* AMBA Plug&Play information on GR-RASTA-ADCDAC */
+ struct ambapp_bus abus;
+ struct ambapp_mmap amba_maps[4];
+ struct ambapp_config config;
+};
+
+struct gr_rasta_adcdac_ver gr_rasta_adcdac_ver0 = {
+ .amba_freq_hz = 50000000,
+ .amba_ioarea = 0x80100000,
+};
+
+int ambapp_rasta_adcdac_int_register(
+ struct drvmgr_dev *dev,
+ int irq,
+ const char *info,
+ drvmgr_isr handler,
+ void *arg);
+int ambapp_rasta_adcdac_int_unregister(
+ struct drvmgr_dev *dev,
+ int irq,
+ drvmgr_isr isr,
+ void *arg);
+int ambapp_rasta_adcdac_int_unmask(
+ struct drvmgr_dev *dev,
+ int irq);
+int ambapp_rasta_adcdac_int_mask(
+ struct drvmgr_dev *dev,
+ int irq);
+int ambapp_rasta_adcdac_int_clear(
+ struct drvmgr_dev *dev,
+ int irq);
+int ambapp_rasta_adcdac_get_params(
+ struct drvmgr_dev *dev,
+ struct drvmgr_bus_params *params);
+
+struct ambapp_ops ambapp_rasta_adcdac_ops = {
+ .int_register = ambapp_rasta_adcdac_int_register,
+ .int_unregister = ambapp_rasta_adcdac_int_unregister,
+ .int_unmask = ambapp_rasta_adcdac_int_unmask,
+ .int_mask = ambapp_rasta_adcdac_int_mask,
+ .int_clear = ambapp_rasta_adcdac_int_clear,
+ .get_params = ambapp_rasta_adcdac_get_params
+};
+
+struct drvmgr_drv_ops gr_rasta_adcdac_ops =
+{ .init = {gr_rasta_adcdac_init1, gr_rasta_adcdac_init2, NULL, NULL},
+ .remove = NULL,
+ .info = NULL
+};
+
+struct pci_dev_id_match gr_rasta_adcdac_ids[] =
+{
+ PCIID_DEVVEND(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_RASTA_ADCDAC),
+ PCIID_END_TABLE /* Mark end of table */
+};
+
+struct pci_drv_info gr_rasta_adcdac_info =
+{
+ {
+ DRVMGR_OBJ_DRV, /* Driver */
+ NULL, /* Next driver */
+ NULL, /* Device list */
+ DRIVER_PCI_GAISLER_RASTAADCDAC_ID,/* Driver ID */
+ "GR-RASTA-ADCDAC_DRV", /* Driver Name */
+ DRVMGR_BUS_TYPE_PCI, /* Bus Type */
+ &gr_rasta_adcdac_ops,
+ NULL, /* Funcs */
+ 0, /* No devices yet */
+ 0,
+ },
+ &gr_rasta_adcdac_ids[0]
+};
+
+/* Driver resources configuration for the AMBA bus on the GR-RASTA-ADCDAC board.
+ * It is declared weak so that the user may override it from the project file,
+ * if the default settings are not enough.
+ *
+ * The configuration consists of an array of configuration pointers, each
+ * pointer determine the configuration of one GR-RASTA-ADCDAC board. Pointer
+ * zero is for board0, pointer 1 for board1 and so on.
+ *
+ * The array must end with a NULL pointer.
+ */
+struct drvmgr_bus_res *gr_rasta_adcdac_resources[] __attribute__((weak)) =
+{
+ NULL
+};
+int gr_rasta_adcdac_resources_cnt = 0;
+
+void gr_rasta_adcdac_register_drv(void)
+{
+ DBG("Registering GR-RASTA-ADCDAC PCI driver\n");
+ drvmgr_drv_register(&gr_rasta_adcdac_info.general);
+}
+
+void gr_rasta_adcdac_isr (void *arg)
+{
+ struct gr_rasta_adcdac_priv *priv = arg;
+ unsigned int status, tmp;
+ int irq;
+ tmp = status = priv->irq->ipend;
+
+ /* DBG("GR-RASTA-ADCDAC: IRQ 0x%x\n",status); */
+
+ for(irq=0; irq<16; irq++) {
+ if ( status & (1<<irq) ) {
+ genirq_doirq(priv->genirq, irq);
+ priv->irq->iclear = (1<<irq);
+ status &= ~(1<<irq);
+ if ( status == 0 )
+ break;
+ }
+ }
+
+ /* ACK interrupt, this is because PCI is Level, so the IRQ Controller still drives the IRQ. */
+ if ( tmp )
+ drvmgr_interrupt_clear(priv->dev, 0);
+
+ DBG("RASTA-ADCDAC-IRQ: 0x%x\n", tmp);
+}
+
+int gr_rasta_adcdac_hw_init1(struct gr_rasta_adcdac_priv *priv)
+{
+ uint32_t data;
+ unsigned int *page0 = NULL;
+ struct ambapp_dev *tmp;
+ int status;
+ struct ambapp_ahb_info *ahb;
+ struct pci_dev_info *devinfo = priv->devinfo;
+ uint32_t bar0, bar0_size;
+
+ /* Select version of GR-RASTA-ADCDAC board */
+ switch (devinfo->rev) {
+ case 0:
+ priv->version = &gr_rasta_adcdac_ver0;
+ break;
+ default:
+ return -2;
+ }
+
+ bar0 = devinfo->resources[0].address;
+ bar0_size = devinfo->resources[0].size;
+ page0 = (unsigned int *)(bar0 + bar0_size/2);
+
+ /* Point PAGE0 to start of Plug and Play information */
+ *page0 = priv->version->amba_ioarea & 0xf0000000;
+
+ /* set parity error response */
+ pci_cfg_r32(priv->pcidev, PCI_COMMAND, &data);
+ pci_cfg_w32(priv->pcidev, PCI_COMMAND, (data|PCI_COMMAND_PARITY));
+
+ /* Scan AMBA Plug&Play */
+
+ /* AMBA MAP bar0 (in CPU) ==> 0x80000000(remote amba address) */
+ priv->amba_maps[0].size = bar0_size/2;
+ priv->amba_maps[0].local_adr = bar0;
+ priv->amba_maps[0].remote_adr = 0x80000000;
+
+ /* AMBA MAP bar1 (in CPU) ==> 0x40000000(remote amba address) */
+ priv->amba_maps[1].size = devinfo->resources[1].size;
+ priv->amba_maps[1].local_adr = devinfo->resources[1].address;
+ priv->amba_maps[1].remote_adr = 0x40000000;
+
+ /* Addresses not matching with map be untouched */
+ priv->amba_maps[2].size = 0xfffffff0;
+ priv->amba_maps[2].local_adr = 0;
+ priv->amba_maps[2].remote_adr = 0;
+
+ /* Mark end of table */
+ priv->amba_maps[3].size=0;
+ priv->amba_maps[3].local_adr = 0;
+ priv->amba_maps[3].remote_adr = 0;
+
+ /* Start AMBA PnP scan at first AHB bus */
+ /*ambapp_scan(priv->bar0 + (priv->version->amba_ioarea & ~0xf0000000),
+ NULL, &priv->amba_maps[0], NULL, &priv->abus.root, NULL);*/
+ ambapp_scan(&priv->abus,
+ bar0 + (priv->version->amba_ioarea & ~0xf0000000),
+ NULL, &priv->amba_maps[0]);
+
+ /* Initialize Frequency of AMBA bus */
+ ambapp_freq_init(&priv->abus, NULL, priv->version->amba_freq_hz);
+
+ /* Point PAGE0 to start of APB area */
+ *page0 = 0x80000000;
+
+ /* Find GRPCI controller */
+ tmp = (void *)ambapp_for_each(&priv->abus,
+ (OPTIONS_ALL|OPTIONS_APB_SLVS),
+ VENDOR_GAISLER, GAISLER_PCIFBRG,
+ ambapp_find_by_idx, NULL);
+ if ( !tmp ) {
+ return -3;
+ }
+ priv->grpci = (struct grpci_regs *)((struct ambapp_apb_info *)tmp->devinfo)->start;
+
+ /* Set GRPCI mmap so that AMBA masters can access CPU-RAM over
+ * the PCI window.
+ */
+ priv->grpci->cfg_stat = (priv->grpci->cfg_stat & 0x0fffffff) |
+ (priv->ahbmst2pci_map & 0xf0000000);
+ priv->grpci->page1 = 0x40000000;
+
+ /* Find IRQ controller */
+ tmp = (void *)ambapp_for_each(&priv->abus,
+ (OPTIONS_ALL|OPTIONS_APB_SLVS),
+ VENDOR_GAISLER, GAISLER_IRQMP,
+ ambapp_find_by_idx, NULL);
+ if ( !tmp ) {
+ return -4;
+ }
+ priv->irq = (struct irqmp_regs *)DEV_TO_APB(tmp)->start;
+ /* Set up GR-RASTA-ADCDAC irq controller */
+ priv->irq->iclear = 0xffff;
+ priv->irq->ilevel = 0;
+ priv->irq->mask[0] = 0;
+
+ /* DOWN streams translation table */
+ priv->bus_maps_down[0].name = "PCI BAR0 -> AMBA";
+ priv->bus_maps_down[0].size = priv->amba_maps[0].size;
+ priv->bus_maps_down[0].from_adr = (void *)priv->amba_maps[0].local_adr;
+ priv->bus_maps_down[0].to_adr = (void *)priv->amba_maps[0].remote_adr;
+
+ priv->bus_maps_down[1].name = "PCI BAR1 -> AMBA";
+ priv->bus_maps_down[1].size = priv->amba_maps[1].size;
+ priv->bus_maps_down[1].from_adr = (void *)priv->amba_maps[1].local_adr;
+ priv->bus_maps_down[1].to_adr = (void *)priv->amba_maps[1].remote_adr;
+
+ /* Mark end of translation table */
+ priv->bus_maps_down[2].size = 0;
+
+ /* Find GRPCI controller AHB Slave interface */
+ tmp = (void *)ambapp_for_each(&priv->abus,
+ (OPTIONS_ALL|OPTIONS_AHB_SLVS),
+ VENDOR_GAISLER, GAISLER_PCIFBRG,
+ ambapp_find_by_idx, NULL);
+ if ( !tmp ) {
+ return -5;
+ }
+ ahb = (struct ambapp_ahb_info *)tmp->devinfo;
+
+ /* UP streams translation table */
+ priv->bus_maps_up[0].name = "AMBA GRPCI Window";
+ priv->bus_maps_up[0].size = ahb->mask[0]; /* AMBA->PCI Window on GR-RASTA-ADCDAC board */
+ priv->bus_maps_up[0].from_adr = (void *)ahb->start[0];
+ priv->bus_maps_up[0].to_adr = (void *)
+ (priv->ahbmst2pci_map & 0xf0000000);
+
+ /* Mark end of translation table */
+ priv->bus_maps_up[1].size = 0;
+
+ /* Successfully registered the RASTA board */
+ return 0;
+}
+
+int gr_rasta_adcdac_hw_init2(struct gr_rasta_adcdac_priv *priv)
+{
+ /* Enable DMA by enabling PCI target as master */
+ pci_master_enable(priv->pcidev);
+
+ return DRVMGR_OK;
+}
+
+/* Called when a PCI target is found with the PCI device and vendor ID
+ * given in gr_rasta_adcdac_ids[].
+ */
+int gr_rasta_adcdac_init1(struct drvmgr_dev *dev)
+{
+ struct gr_rasta_adcdac_priv *priv;
+ struct pci_dev_info *devinfo;
+ int status;
+ uint32_t bar0, bar1, bar0_size, bar1_size;
+ union drvmgr_key_value *value;
+
+ priv = malloc(sizeof(struct gr_rasta_adcdac_priv));
+ if ( !priv )
+ return DRVMGR_NOMEM;
+
+ memset(priv, 0, sizeof(*priv));
+ dev->priv = priv;
+ priv->dev = dev;
+
+ /* Determine number of configurations */
+ if ( gr_rasta_adcdac_resources_cnt == 0 ) {
+ while ( gr_rasta_adcdac_resources[gr_rasta_adcdac_resources_cnt] )
+ gr_rasta_adcdac_resources_cnt++;
+ }
+
+ /* Generate Device prefix */
+
+ strcpy(priv->prefix, "/dev/rastaadcdac0");
+ priv->prefix[16] += dev->minor_drv;
+ mkdir(priv->prefix, S_IRWXU | S_IRWXG | S_IRWXO);
+ priv->prefix[17] = '/';
+ priv->prefix[18] = '\0';
+
+ priv->devinfo = devinfo = (struct pci_dev_info *)dev->businfo;
+ priv->pcidev = devinfo->pcidev;
+ bar0 = devinfo->resources[0].address;
+ bar0_size = devinfo->resources[0].size;
+ bar1 = devinfo->resources[1].address;
+ bar1_size = devinfo->resources[1].size;
+ printf("\n\n--- GR-RASTA-ADCDAC[%d] ---\n", dev->minor_drv);
+ printf(" PCI BUS: 0x%x, SLOT: 0x%x, FUNCTION: 0x%x\n",
+ PCI_DEV_EXPAND(priv->pcidev));
+ printf(" PCI VENDOR: 0x%04x, DEVICE: 0x%04x\n",
+ devinfo->id.vendor, devinfo->id.device);
+ printf(" PCI BAR[0]: 0x%lx - 0x%lx\n", bar0, bar0 + bar0_size - 1);
+ printf(" PCI BAR[1]: 0x%lx - 0x%lx\n", bar1, bar1 + bar1_size - 1);
+ printf(" IRQ: %d\n\n\n", devinfo->irq);
+
+ /* all neccessary space assigned to GR-RASTA-ADCDAC target? */
+ if ((bar0_size == 0) || (bar1_size == 0))
+ return DRVMGR_ENORES;
+
+ /* Let user override which PCI address the AHB masters of the
+ * RASTA-ADCDAC board access when doing DMA to CPU RAM. The AHB masters
+ * access the PCI Window of the AMBA bus, the MSB 4-bits of that address
+ * is translated according this config option before the address
+ * goes out on the PCI bus.
+ * Only the 4 MSB bits have an effect;
+ */
+ value = drvmgr_dev_key_get(priv->dev, "ahbmst2pci", KEY_TYPE_INT);
+ if (value)
+ priv->ahbmst2pci_map = value->i;
+ else
+ priv->ahbmst2pci_map = AHBMST2PCIADR; /* default */
+
+ priv->genirq = genirq_init(16);
+ if ( priv->genirq == NULL ) {
+ free(priv);
+ dev->priv = NULL;
+ return DRVMGR_FAIL;
+ }
+
+ if ( (status = gr_rasta_adcdac_hw_init1(priv)) != 0 ) {
+ genirq_destroy(priv->genirq);
+ free(priv);
+ dev->priv = NULL;
+ printf(" Failed to initialize GR-RASTA-ADCDAC HW: %d\n", status);
+ return DRVMGR_FAIL;
+ }
+
+ /* Init amba bus */
+ priv->config.abus = &priv->abus;
+ priv->config.ops = &ambapp_rasta_adcdac_ops;
+ priv->config.maps_up = &priv->bus_maps_up[0];
+ priv->config.maps_down = &priv->bus_maps_down[0];
+ if ( priv->dev->minor_drv < gr_rasta_adcdac_resources_cnt ) {
+ priv->config.resources = gr_rasta_adcdac_resources[priv->dev->minor_drv];
+ } else {
+ priv->config.resources = NULL;
+ }
+
+ /* Create and register AMBA PnP bus. */
+ return ambapp_bus_register(dev, &priv->config);
+}
+
+int gr_rasta_adcdac_init2(struct drvmgr_dev *dev)
+{
+ struct gr_rasta_adcdac_priv *priv = dev->priv;
+
+ /* Clear any old interrupt requests */
+ drvmgr_interrupt_clear(dev, 0);
+
+ /* Enable System IRQ so that GR-RASTA-ADCDAC PCI target interrupt
+ * goes through.
+ *
+ * It is important to enable it in stage init2. If interrupts were
+ * enabled in init1 this might hang the system when more than one
+ * PCI board is connected, this is because PCI interrupts might
+ * be shared and PCI board 2 have not initialized and might
+ * therefore drive interrupt already when entering init1().
+ */
+ drvmgr_interrupt_register(
+ dev,
+ 0,
+ "gr_rasta_adcdac",
+ gr_rasta_adcdac_isr,
+ (void *)priv);
+
+ return gr_rasta_adcdac_hw_init2(priv);
+}
+
+int ambapp_rasta_adcdac_int_register(
+ struct drvmgr_dev *dev,
+ int irq,
+ const char *info,
+ drvmgr_isr handler,
+ void *arg)
+{
+ struct gr_rasta_adcdac_priv *priv = dev->parent->dev->priv;
+ rtems_interrupt_level level;
+ int status;
+
+ rtems_interrupt_disable(level);
+
+ status = genirq_register(priv->genirq, irq, handler, arg);
+ if ( status == 0 ) {
+ /* Clear IRQ for first registered handler */
+ priv->irq->iclear = (1<<irq);
+ } else if ( status == 1 )
+ status = 0;
+
+ if (status != 0) {
+ rtems_interrupt_enable(level);
+ return DRVMGR_FAIL;
+ }
+
+ status = genirq_enable(priv->genirq, irq, handler, arg);
+ if ( status == 0 ) {
+ /* Enable IRQ for first enabled handler only */
+ priv->irq->mask[0] |= (1<<irq); /* unmask interrupt source */
+ } else if ( status == 1 )
+ status = 0;
+
+ rtems_interrupt_enable(level);
+
+ return status;
+}
+
+int ambapp_rasta_adcdac_int_unregister(
+ struct drvmgr_dev *dev,
+ int irq,
+ drvmgr_isr isr,
+ void *arg)
+{
+ struct gr_rasta_adcdac_priv *priv = dev->parent->dev->priv;
+ rtems_interrupt_level level;
+ int status;
+
+ rtems_interrupt_disable(level);
+
+ status = genirq_disable(priv->genirq, irq, isr, arg);
+ if ( status == 0 ) {
+ /* Disable IRQ only when no enabled handler exists */
+ priv->irq->mask[0] &= ~(1<<irq); /* mask interrupt source */
+ }
+
+ status = genirq_unregister(priv->genirq, irq, isr, arg);
+ if ( status != 0 )
+ status = DRVMGR_FAIL;
+
+ rtems_interrupt_enable(level);
+
+ return status;
+}
+
+int ambapp_rasta_adcdac_int_unmask(
+ struct drvmgr_dev *dev,
+ int irq)
+{
+ struct gr_rasta_adcdac_priv *priv = dev->parent->dev->priv;
+ rtems_interrupt_level level;
+
+ DBG("RASTA-ADCDAC IRQ %d: unmask\n", irq);
+
+ if ( genirq_check(priv->genirq, irq) )
+ return DRVMGR_EINVAL;
+
+ rtems_interrupt_disable(level);
+
+ /* Enable IRQ for first enabled handler only */
+ priv->irq->mask[0] |= (1<<irq); /* unmask interrupt source */
+
+ rtems_interrupt_enable(level);
+
+ return DRVMGR_OK;
+}
+
+int ambapp_rasta_adcdac_int_mask(
+ struct drvmgr_dev *dev,
+ int irq)
+{
+ struct gr_rasta_adcdac_priv *priv = dev->parent->dev->priv;
+ rtems_interrupt_level level;
+
+ DBG("RASTA-ADCDAC IRQ %d: mask\n", irq);
+
+ if ( genirq_check(priv->genirq, irq) )
+ return DRVMGR_EINVAL;
+
+ rtems_interrupt_disable(level);
+
+ /* Disable/mask IRQ */
+ priv->irq->mask[0] &= ~(1<<irq); /* mask interrupt source */
+
+ rtems_interrupt_enable(level);
+
+ return DRVMGR_OK;
+}
+
+int ambapp_rasta_adcdac_int_clear(
+ struct drvmgr_dev *dev,
+ int irq)
+{
+ struct gr_rasta_adcdac_priv *priv = dev->parent->dev->priv;
+
+ if ( genirq_check(priv->genirq, irq) )
+ return DRVMGR_FAIL;
+
+ priv->irq->iclear = (1<<irq);
+
+ return DRVMGR_OK;
+}
+
+int ambapp_rasta_adcdac_get_params(struct drvmgr_dev *dev, struct drvmgr_bus_params *params)
+{
+ struct gr_rasta_adcdac_priv *priv = dev->parent->dev->priv;
+
+ /* Device name prefix pointer, skip /dev */
+ params->dev_prefix = &priv->prefix[5];
+
+ return 0;
+}
+
+void gr_rasta_adcdac_print_dev(struct drvmgr_dev *dev, int options)
+{
+ struct gr_rasta_adcdac_priv *priv = dev->priv;
+ struct pci_dev_info *devinfo = priv->devinfo;
+ uint32_t bar0, bar1, bar0_size, bar1_size;
+
+ /* Print */
+ printf("--- GR-RASTA-ADCDAC [bus 0x%x, dev 0x%x, fun 0x%x] ---\n",
+ PCI_DEV_EXPAND(priv->pcidev));
+
+ bar0 = devinfo->resources[0].address;
+ bar0_size = devinfo->resources[0].size;
+ bar1 = devinfo->resources[1].address;
+ bar1_size = devinfo->resources[1].size;
+
+ printf(" PCI BAR[0]: 0x%lx - 0x%lx\n", bar0, bar0 + bar0_size - 1);
+ printf(" PCI BAR[1]: 0x%lx - 0x%lx\n", bar1, bar1 + bar1_size - 1);
+ printf(" IRQ REGS: 0x%x\n", (unsigned int)priv->irq);
+ printf(" IRQ: %d\n", devinfo->irq);
+ printf(" PCI REVISION: %d\n", devinfo->rev);
+ printf(" FREQ: %d Hz\n", priv->version->amba_freq_hz);
+ printf(" IMASK: 0x%08x\n", priv->irq->mask[0]);
+ printf(" IPEND: 0x%08x\n", priv->irq->ipend);
+
+ /* Print amba config */
+ if ( options & RASTA_ADCDAC_OPTIONS_AMBA ) {
+ ambapp_print(&priv->abus, 10);
+ }
+#if 0
+ /* Print IRQ handlers and their arguments */
+ if ( options & RASTA_ADCDAC_OPTIONS_IRQ ) {
+ int i;
+ for(i=0; i<16; i++) {
+ printf(" IRQ[%02d]: 0x%x, arg: 0x%x\n",
+ i, (unsigned int)priv->isrs[i].handler, (unsigned int)priv->isrs[i].arg);
+ }
+ }
+#endif
+}
+
+void gr_rasta_adcdac_print(int options)
+{
+ struct pci_drv_info *drv = &gr_rasta_adcdac_info;
+ struct drvmgr_dev *dev;
+
+ dev = drv->general.dev;
+ while(dev) {
+ gr_rasta_adcdac_print_dev(dev, options);
+ dev = dev->next_in_drv;
+ }
+}
diff --git a/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_io.c b/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_io.c
new file mode 100644
index 0000000..f96676d
--- /dev/null
+++ b/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_io.c
@@ -0,0 +1,678 @@
+/* GR-RASTA-IO PCI Target driver.
+ *
+ * COPYRIGHT (c) 2008.
+ * Cobham Gaisler AB.
+ *
+ * Configures the GR-RASTA-IO interface PCI board.
+ * This driver provides a AMBA PnP bus by using the general part
+ * of the AMBA PnP bus driver (ambapp_bus.c).
+ *
+ * Driver resources for the AMBA PnP bus provided can be set using
+ * gr_rasta_io_set_resources().
+ *
+ * The license and distribution terms for this file may be
+ * found in found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+
+#include <bsp.h>
+#include <rtems/bspIo.h>
+#include <pci.h>
+
+#include <ambapp.h>
+#include <grlib.h>
+#include <drvmgr/drvmgr.h>
+#include <drvmgr/ambapp_bus.h>
+#include <drvmgr/pci_bus.h>
+#include <genirq.h>
+
+#include <gr_rasta_io.h>
+
+/* Determines which PCI address the AHB masters will access, it should be
+ * set so that the masters can access the CPU RAM. Default is base of CPU RAM,
+ * CPU RAM is mapped 1:1 to PCI space.
+ */
+extern unsigned int _RAM_START;
+#define AHBMST2PCIADR (((unsigned int)&_RAM_START) & 0xf0000000)
+
+/* Offset from 0x80000000 (dual bus version) */
+#define AHB1_BASE_ADDR 0x80000000
+#define AHB1_IOAREA_BASE_ADDR 0x80100000
+
+/* #define DEBUG 1 */
+
+#ifdef DEBUG
+#define DBG(x...) printk(x)
+#else
+#define DBG(x...)
+#endif
+
+/* PCI ID */
+#define PCIID_VENDOR_GAISLER 0x1AC8
+
+int gr_rasta_io_init1(struct drvmgr_dev *dev);
+int gr_rasta_io_init2(struct drvmgr_dev *dev);
+
+struct grpci_regs {
+ volatile unsigned int cfg_stat;
+ volatile unsigned int bar0;
+ volatile unsigned int page0;
+ volatile unsigned int bar1;
+ volatile unsigned int page1;
+ volatile unsigned int iomap;
+ volatile unsigned int stat_cmd;
+};
+
+struct gr_rasta_io_ver {
+ const unsigned int amba_freq_hz; /* The frequency */
+ const unsigned int amba_ioarea; /* The address where the PnP IOAREA starts at */
+};
+
+/* Private data structure for driver */
+struct gr_rasta_io_priv {
+ /* Driver management */
+ struct drvmgr_dev *dev;
+ char prefix[16];
+
+ /* PCI */
+ pci_dev_t pcidev;
+ struct pci_dev_info *devinfo;
+ uint32_t ahbmst2pci_map;
+
+ /* IRQ */
+ genirq_t genirq;
+
+ /* GR-RASTA-IO */
+ struct gr_rasta_io_ver *version;
+ struct irqmp_regs *irq;
+ struct grpci_regs *grpci;
+ struct drvmgr_map_entry bus_maps_down[3];
+ struct drvmgr_map_entry bus_maps_up[2];
+
+ /* AMBA Plug&Play information on GR-RASTA-IO */
+ struct ambapp_bus abus;
+ struct ambapp_mmap amba_maps[4];
+ struct ambapp_config config;
+};
+
+struct gr_rasta_io_ver gr_rasta_io_ver0 = {
+ .amba_freq_hz = 30000000,
+ .amba_ioarea = 0x80100000,
+};
+
+struct gr_rasta_io_ver gr_rasta_io_ver1 = {
+ .amba_freq_hz = 50000000,
+ .amba_ioarea = 0x80100000,
+};
+
+int ambapp_rasta_io_int_register(
+ struct drvmgr_dev *dev,
+ int irq,
+ const char *info,
+ drvmgr_isr handler,
+ void *arg);
+int ambapp_rasta_io_int_unregister(
+ struct drvmgr_dev *dev,
+ int irq,
+ drvmgr_isr handler,
+ void *arg);
+int ambapp_rasta_io_int_unmask(
+ struct drvmgr_dev *dev,
+ int irq);
+int ambapp_rasta_io_int_mask(
+ struct drvmgr_dev *dev,
+ int irq);
+int ambapp_rasta_io_int_clear(
+ struct drvmgr_dev *dev,
+ int irq);
+int ambapp_rasta_io_get_params(
+ struct drvmgr_dev *dev,
+ struct drvmgr_bus_params *params);
+
+struct ambapp_ops ambapp_rasta_io_ops = {
+ .int_register = ambapp_rasta_io_int_register,
+ .int_unregister = ambapp_rasta_io_int_unregister,
+ .int_unmask = ambapp_rasta_io_int_unmask,
+ .int_mask = ambapp_rasta_io_int_mask,
+ .int_clear = ambapp_rasta_io_int_clear,
+ .get_params = ambapp_rasta_io_get_params
+};
+
+struct drvmgr_drv_ops gr_rasta_io_ops =
+{
+ .init = {gr_rasta_io_init1, gr_rasta_io_init2, NULL, NULL},
+ .remove = NULL,
+ .info = NULL
+};
+
+struct pci_dev_id_match gr_rasta_io_ids[] =
+{
+ PCIID_DEVVEND(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_RASTA_IO),
+ PCIID_DEVVEND(PCIID_VENDOR_GAISLER_OLD, PCIID_DEVICE_GR_RASTA_IO_OLD),
+ PCIID_END_TABLE /* Mark end of table */
+};
+
+struct pci_drv_info gr_rasta_io_info =
+{
+ {
+ DRVMGR_OBJ_DRV, /* Driver */
+ NULL, /* Next driver */
+ NULL, /* Device list */
+ DRIVER_PCI_GAISLER_RASTAIO_ID, /* Driver ID */
+ "GR-RASTA-IO_DRV", /* Driver Name */
+ DRVMGR_BUS_TYPE_PCI, /* Bus Type */
+ &gr_rasta_io_ops,
+ NULL, /* Funcs */
+ 0, /* No devices yet */
+ 0,
+ },
+ &gr_rasta_io_ids[0]
+};
+
+/* Driver resources configuration for the AMBA bus on the GR-RASTA-IO board.
+ * It is declared weak so that the user may override it from the project file,
+ * if the default settings are not enough.
+ *
+ * The configuration consists of an array of configuration pointers, each
+ * pointer determine the configuration of one GR-RASTA-IO board. Pointer
+ * zero is for board0, pointer 1 for board1 and so on.
+ *
+ * The array must end with a NULL pointer.
+ */
+struct drvmgr_bus_res *gr_rasta_io_resources[] __attribute__((weak)) =
+{
+ NULL
+};
+int gr_rasta_io_resources_cnt = 0;
+
+void gr_rasta_io_register_drv(void)
+{
+ DBG("Registering GR-RASTA-IO PCI driver\n");
+ drvmgr_drv_register(&gr_rasta_io_info.general);
+}
+
+void gr_rasta_io_isr (void *arg)
+{
+ struct gr_rasta_io_priv *priv = arg;
+ unsigned int status, tmp;
+ int irq;
+ tmp = status = priv->irq->ipend;
+
+ /* DBG("GR-RASTA-IO: IRQ 0x%x\n",status); */
+
+ for(irq=0; irq<16; irq++) {
+ if ( status & (1<<irq) ) {
+ genirq_doirq(priv->genirq, irq);
+ priv->irq->iclear = (1<<irq);
+ status &= ~(1<<irq);
+ if ( status == 0 )
+ break;
+ }
+ }
+
+ /* ACK interrupt, this is because PCI is Level, so the IRQ Controller still drives the IRQ. */
+ if ( tmp )
+ drvmgr_interrupt_clear(priv->dev, 0);
+
+ DBG("RASTA-IO-IRQ: 0x%x\n", tmp);
+}
+
+int gr_rasta_io_hw_init(struct gr_rasta_io_priv *priv)
+{
+ unsigned int *page0 = NULL;
+ struct ambapp_dev *tmp;
+ int status;
+ struct ambapp_ahb_info *ahb;
+ struct pci_dev_info *devinfo = priv->devinfo;
+ uint32_t bar0, bar0_size;
+
+ /* Select version of GR-RASTA-IO board */
+ switch (devinfo->rev) {
+ case 0:
+ priv->version = &gr_rasta_io_ver0;
+ break;
+ case 1:
+ priv->version = &gr_rasta_io_ver1;
+ break;
+ default:
+ return -2;
+ }
+
+ bar0 = devinfo->resources[0].address;
+ bar0_size = devinfo->resources[0].size;
+ page0 = (unsigned int *)(bar0 + bar0_size/2);
+
+ /* Point PAGE0 to start of Plug and Play information */
+ *page0 = priv->version->amba_ioarea & 0xf0000000;
+
+#if 0
+ {
+ uint32_t data;
+ /* set parity error response */
+ pci_cfg_r32(priv->pcidev, PCI_COMMAND, &data);
+ pci_cfg_w32(priv->pcidev, PCI_COMMAND, (data|PCI_COMMAND_PARITY));
+ }
+#endif
+
+ /* Scan AMBA Plug&Play */
+
+ /* AMBA MAP bar0 (in CPU) ==> 0x80000000(remote amba address) */
+ priv->amba_maps[0].size = bar0_size/2;
+ priv->amba_maps[0].local_adr = bar0;
+ priv->amba_maps[0].remote_adr = 0x80000000;
+
+ /* AMBA MAP bar1 (in CPU) ==> 0x40000000(remote amba address) */
+ priv->amba_maps[1].size = devinfo->resources[1].size;
+ priv->amba_maps[1].local_adr = devinfo->resources[1].address;
+ priv->amba_maps[1].remote_adr = 0x40000000;
+
+ /* Addresses not matching with map be untouched */
+ priv->amba_maps[2].size = 0xfffffff0;
+ priv->amba_maps[2].local_adr = 0;
+ priv->amba_maps[2].remote_adr = 0;
+
+ /* Mark end of table */
+ priv->amba_maps[3].size=0;
+ priv->amba_maps[3].local_adr = 0;
+ priv->amba_maps[3].remote_adr = 0;
+
+ /* Start AMBA PnP scan at first AHB bus */
+ ambapp_scan(&priv->abus,
+ bar0 + (priv->version->amba_ioarea & ~0xf0000000),
+ NULL, &priv->amba_maps[0]);
+
+ /* Initialize Frequency of AMBA bus */
+ ambapp_freq_init(&priv->abus, NULL, priv->version->amba_freq_hz);
+
+ /* Point PAGE0 to start of APB area */
+ *page0 = 0x80000000;
+
+ /* Find GRPCI controller */
+ tmp = (void *)ambapp_for_each(&priv->abus,
+ (OPTIONS_ALL|OPTIONS_APB_SLVS),
+ VENDOR_GAISLER, GAISLER_PCIFBRG,
+ ambapp_find_by_idx, NULL);
+ if ( !tmp ) {
+ return -3;
+ }
+ priv->grpci = (struct grpci_regs *)((struct ambapp_apb_info *)tmp->devinfo)->start;
+
+ /* Set GRPCI mmap so that AMBA masters can access CPU-RAM over
+ * the PCI window.
+ */
+ priv->grpci->cfg_stat = (priv->grpci->cfg_stat & 0x0fffffff) |
+ (priv->ahbmst2pci_map & 0xf0000000);
+ priv->grpci->page1 = 0x40000000;
+
+ /* Find IRQ controller, Clear all current IRQs */
+ tmp = (void *)ambapp_for_each(&priv->abus,
+ (OPTIONS_ALL|OPTIONS_APB_SLVS),
+ VENDOR_GAISLER, GAISLER_IRQMP,
+ ambapp_find_by_idx, NULL);
+ if ( !tmp ) {
+ return -4;
+ }
+ priv->irq = (struct irqmp_regs *)DEV_TO_APB(tmp)->start;
+ /* Set up GR-RASTA-IO irq controller */
+ priv->irq->mask[0] = 0;
+ priv->irq->iclear = 0xffff;
+ priv->irq->ilevel = 0;
+
+ /* DOWN streams translation table */
+ priv->bus_maps_down[0].name = "PCI BAR0 -> AMBA";
+ priv->bus_maps_down[0].size = priv->amba_maps[0].size;
+ priv->bus_maps_down[0].from_adr = (void *)priv->amba_maps[0].local_adr;
+ priv->bus_maps_down[0].to_adr = (void *)priv->amba_maps[0].remote_adr;
+
+ priv->bus_maps_down[1].name = "PCI BAR1 -> AMBA";
+ priv->bus_maps_down[1].size = priv->amba_maps[1].size;
+ priv->bus_maps_down[1].from_adr = (void *)priv->amba_maps[1].local_adr;
+ priv->bus_maps_down[1].to_adr = (void *)priv->amba_maps[1].remote_adr;
+
+ /* Mark end of translation table */
+ priv->bus_maps_down[2].size = 0;
+
+ /* Find GRPCI controller AHB Slave interface */
+ tmp = (void *)ambapp_for_each(&priv->abus,
+ (OPTIONS_ALL|OPTIONS_AHB_SLVS),
+ VENDOR_GAISLER, GAISLER_PCIFBRG,
+ ambapp_find_by_idx, NULL);
+ if ( !tmp ) {
+ return -5;
+ }
+ ahb = (struct ambapp_ahb_info *)tmp->devinfo;
+
+ /* UP streams translation table */
+ priv->bus_maps_up[0].name = "AMBA GRPCI Window";
+ priv->bus_maps_up[0].size = ahb->mask[0]; /* AMBA->PCI Window on GR-RASTA-IO board */
+ priv->bus_maps_up[0].from_adr = (void *)ahb->start[0];
+ priv->bus_maps_up[0].to_adr = (void *)
+ (priv->ahbmst2pci_map & 0xf0000000);
+
+ /* Mark end of translation table */
+ priv->bus_maps_up[1].size = 0;
+
+ /* Successfully registered the RASTA board */
+ return 0;
+}
+
+int gr_rasta_io_hw_init2(struct gr_rasta_io_priv *priv)
+{
+ /* Enable DMA by enabling PCI target as master */
+ pci_master_enable(priv->pcidev);
+
+ return DRVMGR_OK;
+}
+
+/* Called when a PCI target is found with the PCI device and vendor ID
+ * given in gr_rasta_io_ids[].
+ */
+int gr_rasta_io_init1(struct drvmgr_dev *dev)
+{
+ struct gr_rasta_io_priv *priv;
+ struct pci_dev_info *devinfo;
+ int status;
+ uint32_t bar0, bar1, bar0_size, bar1_size;
+ union drvmgr_key_value *value;
+
+ priv = malloc(sizeof(struct gr_rasta_io_priv));
+ if ( !priv )
+ return DRVMGR_NOMEM;
+
+ memset(priv, 0, sizeof(*priv));
+ dev->priv = priv;
+ priv->dev = dev;
+
+ /* Determine number of configurations */
+ if ( gr_rasta_io_resources_cnt == 0 ) {
+ while ( gr_rasta_io_resources[gr_rasta_io_resources_cnt] )
+ gr_rasta_io_resources_cnt++;
+ }
+
+ /* Generate Device prefix */
+
+ strcpy(priv->prefix, "/dev/rastaio0");
+ priv->prefix[12] += dev->minor_drv;
+ mkdir(priv->prefix, S_IRWXU | S_IRWXG | S_IRWXO);
+ priv->prefix[13] = '/';
+ priv->prefix[14] = '\0';
+
+ priv->devinfo = devinfo = (struct pci_dev_info *)dev->businfo;
+ priv->pcidev = devinfo->pcidev;
+ bar0 = devinfo->resources[0].address;
+ bar0_size = devinfo->resources[0].size;
+ bar1 = devinfo->resources[1].address;
+ bar1_size = devinfo->resources[1].size;
+ printf("\n\n--- GR-RASTA-IO[%d] ---\n", dev->minor_drv);
+ printf(" PCI BUS: 0x%x, SLOT: 0x%x, FUNCTION: 0x%x\n",
+ PCI_DEV_EXPAND(priv->pcidev));
+ printf(" PCI VENDOR: 0x%04x, DEVICE: 0x%04x\n",
+ devinfo->id.vendor, devinfo->id.device);
+ printf(" PCI BAR[0]: 0x%lx - 0x%lx\n", bar0, bar0 + bar0_size - 1);
+ printf(" PCI BAR[1]: 0x%lx - 0x%lx\n", bar1, bar1 + bar1_size - 1);
+ printf(" IRQ: %d\n\n\n", devinfo->irq);
+
+ /* all neccessary space assigned to GR-RASTA-IO target? */
+ if ((bar0_size == 0) || (bar1_size == 0))
+ return DRVMGR_ENORES;
+
+ /* Let user override which PCI address the AHB masters of the
+ * GR-RASTA-IO board access when doing DMA to CPU RAM. The AHB masters
+ * access the PCI Window of the AMBA bus, the MSB 4-bits of that address
+ * is translated according this config option before the address
+ * goes out on the PCI bus.
+ * Only the 4 MSB bits have an effect;
+ */
+ value = drvmgr_dev_key_get(priv->dev, "ahbmst2pci", KEY_TYPE_INT);
+ if (value)
+ priv->ahbmst2pci_map = value->i;
+ else
+ priv->ahbmst2pci_map = AHBMST2PCIADR; /* default */
+
+ priv->genirq = genirq_init(16);
+ if ( priv->genirq == NULL ) {
+ free(priv);
+ dev->priv = NULL;
+ return DRVMGR_FAIL;
+ }
+
+ status = gr_rasta_io_hw_init(priv);
+ if ( status != 0 ) {
+ genirq_destroy(priv->genirq);
+ free(priv);
+ dev->priv = NULL;
+ printf(" Failed to initialize GR-RASTA-IO HW: %d\n", status);
+ return DRVMGR_FAIL;
+ }
+
+ /* Init amba bus */
+ priv->config.abus = &priv->abus;
+ priv->config.ops = &ambapp_rasta_io_ops;
+ priv->config.maps_up = &priv->bus_maps_up[0];
+ priv->config.maps_down = &priv->bus_maps_down[0];
+ if ( priv->dev->minor_drv < gr_rasta_io_resources_cnt ) {
+ priv->config.resources = gr_rasta_io_resources[priv->dev->minor_drv];
+ } else {
+ priv->config.resources = NULL;
+ }
+
+ /* Create and register AMBA PnP bus. */
+ return ambapp_bus_register(dev, &priv->config);
+}
+
+int gr_rasta_io_init2(struct drvmgr_dev *dev)
+{
+ struct gr_rasta_io_priv *priv = dev->priv;
+
+ /* Clear any old interrupt requests */
+ drvmgr_interrupt_clear(dev, 0);
+
+ /* Enable System IRQ so that GR-RASTA-IO PCI target interrupt goes
+ * through.
+ *
+ * It is important to enable it in stage init2. If interrupts were
+ * enabled in init1 this might hang the system when more than one
+ * PCI board is connected, this is because PCI interrupts might
+ * be shared and PCI board 2 have not initialized and
+ * might therefore drive interrupt already when entering init1().
+ */
+ drvmgr_interrupt_register(
+ dev,
+ 0,
+ "gr_rasta_io",
+ gr_rasta_io_isr,
+ (void *)priv);
+
+ return gr_rasta_io_hw_init2(priv);
+}
+
+int ambapp_rasta_io_int_register(
+ struct drvmgr_dev *dev,
+ int irq,
+ const char *info,
+ drvmgr_isr handler,
+ void *arg)
+{
+ struct gr_rasta_io_priv *priv = dev->parent->dev->priv;
+ rtems_interrupt_level level;
+ int status;
+
+ rtems_interrupt_disable(level);
+
+ status = genirq_register(priv->genirq, irq, handler, arg);
+ if ( status == 0 ) {
+ /* Clear IRQ for first registered handler */
+ priv->irq->iclear = (1<<irq);
+ } else if ( status == 1 )
+ status = 0;
+
+ if (status != 0) {
+ rtems_interrupt_enable(level);
+ return DRVMGR_FAIL;
+ }
+
+ status = genirq_enable(priv->genirq, irq, handler, arg);
+ if ( status == 0 ) {
+ /* Enable IRQ for first enabled handler only */
+ priv->irq->mask[0] |= (1<<irq); /* unmask interrupt source */
+ } else if ( status == 1 )
+ status = 0;
+
+ rtems_interrupt_enable(level);
+
+ return status;
+}
+
+int ambapp_rasta_io_int_unregister(
+ struct drvmgr_dev *dev,
+ int irq,
+ drvmgr_isr isr,
+ void *arg)
+{
+ struct gr_rasta_io_priv *priv = dev->parent->dev->priv;
+ rtems_interrupt_level level;
+ int status;
+
+ rtems_interrupt_disable(level);
+
+ status = genirq_disable(priv->genirq, irq, isr, arg);
+ if ( status == 0 ) {
+ /* Disable IRQ only when no enabled handler exists */
+ priv->irq->mask[0] &= ~(1<<irq); /* mask interrupt source */
+ }
+
+ status = genirq_unregister(priv->genirq, irq, isr, arg);
+ if ( status != 0 )
+ status = DRVMGR_FAIL;
+
+ rtems_interrupt_enable(level);
+
+ return status;
+}
+
+int ambapp_rasta_io_int_unmask(
+ struct drvmgr_dev *dev,
+ int irq)
+{
+ struct gr_rasta_io_priv *priv = dev->parent->dev->priv;
+ rtems_interrupt_level level;
+
+ DBG("RASTA-IO IRQ %d: unmask\n", irq);
+
+ if ( genirq_check(priv->genirq, irq) )
+ return DRVMGR_EINVAL;
+
+ rtems_interrupt_disable(level);
+
+ /* Enable IRQ for first enabled handler only */
+ priv->irq->mask[0] |= (1<<irq); /* unmask interrupt source */
+
+ rtems_interrupt_enable(level);
+
+ return DRVMGR_OK;
+}
+
+int ambapp_rasta_io_int_mask(
+ struct drvmgr_dev *dev,
+ int irq)
+{
+ struct gr_rasta_io_priv *priv = dev->parent->dev->priv;
+ rtems_interrupt_level level;
+
+ DBG("RASTA-IO IRQ %d: mask\n", irq);
+
+ if ( genirq_check(priv->genirq, irq) )
+ return DRVMGR_EINVAL;
+
+ rtems_interrupt_disable(level);
+
+ /* Disable/mask IRQ */
+ priv->irq->mask[0] &= ~(1<<irq); /* mask interrupt source */
+
+ rtems_interrupt_enable(level);
+
+ return DRVMGR_OK;
+}
+
+int ambapp_rasta_io_int_clear(
+ struct drvmgr_dev *dev,
+ int irq)
+{
+ struct gr_rasta_io_priv *priv = dev->parent->dev->priv;
+
+ if ( genirq_check(priv->genirq, irq) )
+ return DRVMGR_EINVAL;
+
+ priv->irq->iclear = (1<<irq);
+
+ return DRVMGR_OK;
+}
+
+int ambapp_rasta_io_get_params(struct drvmgr_dev *dev, struct drvmgr_bus_params *params)
+{
+ struct gr_rasta_io_priv *priv = dev->parent->dev->priv;
+
+ /* Device name prefix pointer, skip /dev */
+ params->dev_prefix = &priv->prefix[5];
+
+ return 0;
+}
+
+void gr_rasta_io_print_dev(struct drvmgr_dev *dev, int options)
+{
+ struct gr_rasta_io_priv *priv = dev->priv;
+ struct pci_dev_info *devinfo = priv->devinfo;
+ uint32_t bar0, bar1, bar0_size, bar1_size;
+
+ /* Print */
+ printf("--- GR-RASTA-IO [bus 0x%x, dev 0x%x, fun 0x%x] ---\n",
+ PCI_DEV_EXPAND(priv->pcidev));
+
+ bar0 = devinfo->resources[0].address;
+ bar0_size = devinfo->resources[0].size;
+ bar1 = devinfo->resources[1].address;
+ bar1_size = devinfo->resources[1].size;
+
+ printf(" PCI BAR[0]: 0x%lx - 0x%lx\n", bar0, bar0 + bar0_size - 1);
+ printf(" PCI BAR[1]: 0x%lx - 0x%lx\n", bar1, bar1 + bar1_size - 1);
+ printf(" IRQ REGS: 0x%x\n", (unsigned int)priv->irq);
+ printf(" IRQ: %d\n", devinfo->irq);
+ printf(" PCI REVISION: %d\n", devinfo->rev);
+ printf(" FREQ: %d Hz\n", priv->version->amba_freq_hz);
+ printf(" IMASK: 0x%08x\n", priv->irq->mask[0]);
+ printf(" IPEND: 0x%08x\n", priv->irq->ipend);
+
+ /* Print amba config */
+ if ( options & RASTA_IO_OPTIONS_AMBA ) {
+ ambapp_print(&priv->abus, 10);
+ }
+
+#if 0
+ /* Print IRQ handlers and their arguments */
+ if ( options & RASTA_IO_OPTIONS_IRQ ) {
+ int i;
+ for(i=0; i<16; i++) {
+ printf(" IRQ[%02d]: 0x%x, arg: 0x%x\n",
+ i, (unsigned int)priv->isrs[i].handler, (unsigned int)priv->isrs[i].arg);
+ }
+ }
+#endif
+}
+
+void gr_rasta_io_print(int options)
+{
+ struct pci_drv_info *drv = &gr_rasta_io_info;
+ struct drvmgr_dev *dev;
+
+ dev = drv->general.dev;
+ while(dev) {
+ gr_rasta_io_print_dev(dev, options);
+ dev = dev->next_in_drv;
+ }
+}
diff --git a/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_spw_router.c b/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_spw_router.c
new file mode 100644
index 0000000..027c1d4
--- /dev/null
+++ b/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_spw_router.c
@@ -0,0 +1,675 @@
+/* GR-RASTA-SPW-ROUTER PCI Target driver.
+ *
+ * COPYRIGHT (c) 2011.
+ * Cobham Gaisler AB.
+ *
+ * The license and distribution terms for this file may be
+ * found in found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ *
+ * Configures the GR-RASTA-SPW-ROUTER interface PCI board.
+ * This driver provides a AMBA PnP bus by using the general part
+ * of the AMBA PnP bus driver (ambapp_bus.c). Based on the
+ * GR-RASTA-IO driver.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+
+#include <bsp.h>
+#include <rtems/bspIo.h>
+#include <pci.h>
+
+#include <ambapp.h>
+#include <grlib.h>
+#include <drvmgr/drvmgr.h>
+#include <drvmgr/ambapp_bus.h>
+#include <drvmgr/pci_bus.h>
+#include <genirq.h>
+
+/*#include <gr_rasta_spw_router.h> */
+
+/* Determines which PCI address the AHB masters will access, it should be
+ * set so that the masters can access the CPU RAM. Default is base of CPU RAM,
+ * CPU RAM is mapped 1:1 to PCI space.
+ */
+extern unsigned int _RAM_START;
+#define AHBMST2PCIADR (((unsigned int)&_RAM_START) & 0xf0000000)
+
+/* Offset from 0x80000000 (dual bus version) */
+#define AHB1_BASE_ADDR 0x80000000
+#define AHB1_IOAREA_BASE_ADDR 0x80100000
+
+#define GRPCI2_BAR0_TO_AHB_MAP 0x04 /* Fixme */
+#define GRPCI2_PCI_CONFIG 0x20 /* Fixme */
+#define RASTA_SPW_ROUTER_OPTIONS_AMBA 0x01 /* Print AMBA bus devices */ /* Fixme */
+#define RASTA_SPW_ROUTER_OPTIONS_IRQ 0x02 /* Print current IRQ setup */ /* Fixme */
+
+
+/* #define DEBUG 1 */
+
+#ifdef DEBUG
+#define DBG(x...) printk(x)
+#else
+#define DBG(x...)
+#endif
+
+/* PCI ID */
+#define PCIID_VENDOR_GAISLER 0x1AC8
+
+int gr_rasta_spw_router_init1(struct drvmgr_dev *dev);
+int gr_rasta_spw_router_init2(struct drvmgr_dev *dev);
+
+struct grpci2_regs {
+ volatile unsigned int ctrl;
+ volatile unsigned int statcap;
+ volatile unsigned int pcimstprefetch;
+ volatile unsigned int ahbtopciiomap;
+ volatile unsigned int dmactrl;
+ volatile unsigned int dmadesc;
+ volatile unsigned int dmachanact;
+ volatile unsigned int reserved;
+ volatile unsigned int pcibartoahb[6];
+ volatile unsigned int reserved2[2];
+ volatile unsigned int ahbtopcimemmap[16];
+ volatile unsigned int trcctrl;
+ volatile unsigned int trccntmode;
+ volatile unsigned int trcadpat;
+ volatile unsigned int trcadmask;
+ volatile unsigned int trcctrlsigpat;
+ volatile unsigned int trcctrlsigmask;
+ volatile unsigned int trcadstate;
+ volatile unsigned int trcctrlsigstate;
+};
+
+struct gr_rasta_spw_router_ver {
+ const unsigned int amba_freq_hz; /* The frequency */
+ const unsigned int amba_ioarea; /* The address where the PnP IOAREA starts at */
+};
+
+/* Private data structure for driver */
+struct gr_rasta_spw_router_priv {
+ /* Driver management */
+ struct drvmgr_dev *dev;
+ char prefix[20];
+
+ /* PCI */
+ pci_dev_t pcidev;
+ struct pci_dev_info *devinfo;
+ uint32_t ahbmst2pci_map;
+
+ /* IRQ */
+ genirq_t genirq;
+
+ /* GR-RASTA-SPW-ROUTER */
+ struct gr_rasta_spw_router_ver *version;
+ struct irqmp_regs *irq;
+ struct grpci2_regs *grpci2;
+ struct drvmgr_map_entry bus_maps_up[2];
+ struct drvmgr_map_entry bus_maps_down[2];
+
+ /* AMBA Plug&Play information on GR-RASTA-SPW-ROUTER */
+ struct ambapp_bus abus;
+ struct ambapp_mmap amba_maps[3];
+ struct ambapp_config config;
+};
+
+struct gr_rasta_spw_router_ver gr_rasta_spw_router_ver0 = {
+ .amba_freq_hz = 50000000,
+ .amba_ioarea = 0xfff00000,
+};
+
+int ambapp_rasta_spw_router_int_register(
+ struct drvmgr_dev *dev,
+ int irq,
+ const char *info,
+ drvmgr_isr handler,
+ void *arg);
+int ambapp_rasta_spw_router_int_unregister(
+ struct drvmgr_dev *dev,
+ int irq,
+ drvmgr_isr handler,
+ void *arg);
+int ambapp_rasta_spw_router_int_unmask(
+ struct drvmgr_dev *dev,
+ int irq);
+int ambapp_rasta_spw_router_int_mask(
+ struct drvmgr_dev *dev,
+ int irq);
+int ambapp_rasta_spw_router_int_clear(
+ struct drvmgr_dev *dev,
+ int irq);
+int ambapp_rasta_spw_router_get_params(
+ struct drvmgr_dev *dev,
+ struct drvmgr_bus_params *params);
+
+struct ambapp_ops ambapp_rasta_spw_router_ops = {
+ .int_register = ambapp_rasta_spw_router_int_register,
+ .int_unregister = ambapp_rasta_spw_router_int_unregister,
+ .int_unmask = ambapp_rasta_spw_router_int_unmask,
+ .int_mask = ambapp_rasta_spw_router_int_mask,
+ .int_clear = ambapp_rasta_spw_router_int_clear,
+ .get_params = ambapp_rasta_spw_router_get_params
+};
+
+struct drvmgr_drv_ops gr_rasta_spw_router_ops =
+{
+ .init = {gr_rasta_spw_router_init1, gr_rasta_spw_router_init2, NULL, NULL},
+ .remove = NULL,
+ .info = NULL
+};
+
+struct pci_dev_id_match gr_rasta_spw_router_ids[] =
+{
+ PCIID_DEVVEND(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_RASTA_SPW_RTR),
+ PCIID_END_TABLE /* Mark end of table */
+};
+
+struct pci_drv_info gr_rasta_spw_router_info =
+{
+ {
+ DRVMGR_OBJ_DRV, /* Driver */
+ NULL, /* Next driver */
+ NULL, /* Device list */
+ DRIVER_PCI_GAISLER_RASTA_SPW_ROUTER_ID, /* Driver ID */
+ "GR-RASTA-SPW_ROUTER_DRV", /* Driver Name */
+ DRVMGR_BUS_TYPE_PCI, /* Bus Type */
+ &gr_rasta_spw_router_ops,
+ NULL, /* Funcs */
+ 0, /* No devices yet */
+ sizeof(struct gr_rasta_spw_router_priv),
+ },
+ &gr_rasta_spw_router_ids[0]
+};
+
+/* Driver resources configuration for the AMBA bus on the GR-RASTA-SPW-ROUTER board.
+ * It is declared weak so that the user may override it from the project file,
+ * if the default settings are not enough.
+ *
+ * The configuration consists of an array of configuration pointers, each
+ * pointer determine the configuration of one GR-RASTA-SPW-ROUTER board. Pointer
+ * zero is for board0, pointer 1 for board1 and so on.
+ *
+ * The array must end with a NULL pointer.
+ */
+struct drvmgr_bus_res *gr_rasta_spw_router_resources[] __attribute__((weak)) =
+{
+ NULL
+};
+int gr_rasta_spw_router_resources_cnt = 0;
+
+void gr_rasta_spw_router_register_drv(void)
+{
+ DBG("Registering GR-RASTA-SPW-ROUTER PCI driver\n");
+ drvmgr_drv_register(&gr_rasta_spw_router_info.general);
+}
+
+void gr_rasta_spw_router_isr(void *arg)
+{
+ struct gr_rasta_spw_router_priv *priv = arg;
+ unsigned int status, tmp;
+ int irq;
+ tmp = status = priv->irq->ipend;
+
+ /* DBG("GR-RASTA-SPW-ROUTER: IRQ 0x%x\n",status); */
+
+ for(irq=0; irq<16; irq++) {
+ if ( status & (1<<irq) ) {
+ genirq_doirq(priv->genirq, irq);
+ priv->irq->iclear = (1<<irq);
+ status &= ~(1<<irq);
+ if ( status == 0 )
+ break;
+ }
+ }
+
+ /* ACK interrupt, this is because PCI is Level, so the IRQ Controller
+ * still drives the IRQ
+ */
+ if ( tmp )
+ drvmgr_interrupt_clear(priv->dev, 0);
+
+ DBG("RASTA-SPW_ROUTER-IRQ: 0x%x\n", tmp);
+}
+
+int gr_rasta_spw_router_hw_init(struct gr_rasta_spw_router_priv *priv)
+{
+ int i;
+ uint32_t data;
+ unsigned int ctrl;
+ uint8_t tmp2;
+ struct ambapp_dev *tmp;
+ int status;
+ struct ambapp_ahb_info *ahb;
+ uint8_t cap_ptr;
+ pci_dev_t pcidev = priv->pcidev;
+ struct pci_dev_info *devinfo = priv->devinfo;
+
+ /* Select version of GR-RASTA-SPW-ROUTER board. Currently only one
+ * version
+ */
+ switch (devinfo->rev) {
+ case 0:
+ priv->version = &gr_rasta_spw_router_ver0;
+ break;
+ default:
+ return -2;
+ }
+
+ /* Check capabilities list bit */
+ pci_cfg_r8(pcidev, PCI_STATUS, &tmp2);
+
+ if (!((tmp2 >> 4) & 1)) {
+ /* Capabilities list not available which it should be in the GRPCI2 */
+ return -3;
+ }
+
+ /* Read capabilities pointer */
+ pci_cfg_r8(pcidev, PCI_CAP_PTR, &cap_ptr);
+
+ /* Set AHB address mappings for target PCI bars */
+ pci_cfg_w32(pcidev, cap_ptr+GRPCI2_BAR0_TO_AHB_MAP, 0xffe00000); /* APB bus, AHB I/O bus 2 MB */
+
+ /* Set PCI bus to be big endian */
+ pci_cfg_r32(pcidev, cap_ptr+GRPCI2_PCI_CONFIG, &data);
+ data = data & 0xFFFFFFFE;
+ pci_cfg_w32(pcidev, cap_ptr+GRPCI2_PCI_CONFIG, data);
+
+#if 0
+ /* set parity error response */
+ pci_cfg_r32(pcidev, PCI_COMMAND, &data);
+ pci_cfg_w32(pcidev, PCI_COMMAND, (data|PCI_COMMAND_PARITY));
+#endif
+
+ /* Scan AMBA Plug&Play */
+
+ /* AMBA MAP bar0 (in router) ==> 0xffe00000(remote amba address) */
+ priv->amba_maps[0].size = devinfo->resources[0].size;
+ priv->amba_maps[0].local_adr = devinfo->resources[0].address;
+ priv->amba_maps[0].remote_adr = 0xffe00000;
+
+ /* Addresses not matching with map be untouched */
+ priv->amba_maps[1].size = 0xfffffff0;
+ priv->amba_maps[1].local_adr = 0;
+ priv->amba_maps[1].remote_adr = 0;
+
+ /* Mark end of table */
+ priv->amba_maps[2].size=0;
+
+ /* Start AMBA PnP scan at first AHB bus */
+ ambapp_scan(
+ &priv->abus,
+ devinfo->resources[0].address + 0x100000,
+ NULL,
+ &priv->amba_maps[0]);
+
+ /* Initialize Frequency of AMBA bus */
+ ambapp_freq_init(&priv->abus, NULL, priv->version->amba_freq_hz);
+
+ /* Find IRQ controller, Clear all current IRQs */
+ tmp = ambapp_for_each(&priv->abus,
+ (OPTIONS_ALL|OPTIONS_APB_SLVS),
+ VENDOR_GAISLER, GAISLER_IRQMP,
+ ambapp_find_by_idx, NULL);
+ if ( !tmp ) {
+ return -4;
+ }
+ priv->irq = (struct irqmp_regs *)DEV_TO_APB(tmp)->start;
+ /* Set up GR-RASTA-SPW-ROUTER irq controller */
+ priv->irq->mask[0] = 0;
+ priv->irq->iclear = 0xffff;
+ priv->irq->ilevel = 0;
+
+ priv->bus_maps_down[0].name = "PCI BAR0 -> AMBA";
+ priv->bus_maps_down[0].size = priv->amba_maps[0].size;
+ priv->bus_maps_down[0].from_adr = (void *)priv->amba_maps[0].local_adr;
+ priv->bus_maps_down[0].to_adr = (void *)priv->amba_maps[0].remote_adr;
+ priv->bus_maps_down[1].size = 0;
+
+ /* Find GRPCI2 controller AHB Slave interface */
+ tmp = (void *)ambapp_for_each(&priv->abus,
+ (OPTIONS_ALL|OPTIONS_AHB_SLVS),
+ VENDOR_GAISLER, GAISLER_GRPCI2,
+ ambapp_find_by_idx, NULL);
+ if ( !tmp ) {
+ return -5;
+ }
+ ahb = (struct ambapp_ahb_info *)tmp->devinfo;
+ priv->bus_maps_up[0].name = "AMBA GRPCI2 Window";
+ priv->bus_maps_up[0].size = ahb->mask[0]; /* AMBA->PCI Window on GR-RASTA-SPW-ROUTER board */
+ priv->bus_maps_up[0].from_adr = (void *)ahb->start[0];
+ priv->bus_maps_up[0].to_adr = (void *)
+ (priv->ahbmst2pci_map & ~(ahb->mask[0]-1));
+ priv->bus_maps_up[1].size = 0;
+
+ /* Find GRPCI2 controller APB Slave interface */
+ tmp = (void *)ambapp_for_each(&priv->abus,
+ (OPTIONS_ALL|OPTIONS_APB_SLVS),
+ VENDOR_GAISLER, GAISLER_GRPCI2,
+ ambapp_find_by_idx, NULL);
+ if ( !tmp ) {
+ return -6;
+ }
+ priv->grpci2 = (struct grpci2_regs *)
+ ((struct ambapp_apb_info *)tmp->devinfo)->start;
+
+ /* Set AHB to PCI mapping for all AMBA AHB masters */
+ for(i = 0; i < 16; i++) {
+ priv->grpci2->ahbtopcimemmap[i] = priv->ahbmst2pci_map &
+ ~(ahb->mask[0]-1);
+ }
+
+ /* Make sure dirq(0) sampling is enabled */
+ ctrl = priv->grpci2->ctrl;
+ ctrl = (ctrl & 0xFFFFFF0F) | (1 << 4);
+ printf("data: 0x%x\n", ctrl);
+ priv->grpci2->ctrl = ctrl;
+
+ /* Successfully registered the RASTA-SPW-ROUTER board */
+ return 0;
+}
+
+int gr_rasta_spw_router_hw_init2(struct gr_rasta_spw_router_priv *priv)
+{
+ /* Enable DMA by enabling PCI target as master */
+ pci_master_enable(priv->pcidev);
+
+ return DRVMGR_OK;
+}
+
+/* Called when a PCI target is found with the PCI device and vendor ID
+ * given in gr_rasta_spw_router_ids[].
+ */
+int gr_rasta_spw_router_init1(struct drvmgr_dev *dev)
+{
+ struct gr_rasta_spw_router_priv *priv;
+ struct pci_dev_info *devinfo;
+ int status;
+ uint32_t bar0, bar0_size;
+ union drvmgr_key_value *value;
+
+ priv = dev->priv;
+ if (!priv)
+ return DRVMGR_NOMEM;
+
+ memset(priv, 0, sizeof(*priv));
+ dev->priv = priv;
+ priv->dev = dev;
+
+ /* Determine number of configurations */
+ if ( gr_rasta_spw_router_resources_cnt == 0 ) {
+ while ( gr_rasta_spw_router_resources[gr_rasta_spw_router_resources_cnt] )
+ gr_rasta_spw_router_resources_cnt++;
+ }
+
+ /* Generate Device prefix */
+
+ strcpy(priv->prefix, "/dev/spwrouter0");
+ priv->prefix[14] += dev->minor_drv;
+ mkdir(priv->prefix, S_IRWXU | S_IRWXG | S_IRWXO);
+ priv->prefix[15] = '/';
+ priv->prefix[16] = '\0';
+
+ priv->devinfo = devinfo = (struct pci_dev_info *)dev->businfo;
+ priv->pcidev = devinfo->pcidev;
+ bar0 = devinfo->resources[0].address;
+ bar0_size = devinfo->resources[0].size;
+ printf("\n\n--- GR-RASTA-SPW-ROUTER[%d] ---\n", dev->minor_drv);
+ printf(" PCI BUS: 0x%x, SLOT: 0x%x, FUNCTION: 0x%x\n",
+ PCI_DEV_EXPAND(priv->pcidev));
+ printf(" PCI VENDOR: 0x%04x, DEVICE: 0x%04x\n",
+ devinfo->id.vendor, devinfo->id.device);
+ printf(" PCI BAR[0]: 0x%08lx - 0x%08lx\n", bar0, bar0 + bar0_size - 1);
+ printf(" IRQ: %d\n\n\n", devinfo->irq);
+
+ /* all neccessary space assigned to GR-RASTA-SPW-ROUTER target? */
+ if (bar0_size == 0)
+ return DRVMGR_ENORES;
+
+ /* Let user override which PCI address the AHB masters of the
+ * GR-RASTA-SPW board access when doing DMA to CPU RAM. The AHB masters
+ * access the PCI Window of the AMBA bus, the MSB 4-bits of that address
+ * is translated according this config option before the address
+ * goes out on the PCI bus.
+ * Only the 4 MSB bits have an effect;
+ */
+ value = drvmgr_dev_key_get(priv->dev, "ahbmst2pci", KEY_TYPE_INT);
+ if (value)
+ priv->ahbmst2pci_map = value->i;
+ else
+ priv->ahbmst2pci_map = AHBMST2PCIADR; /* default */
+
+ priv->genirq = genirq_init(16);
+ if ( priv->genirq == NULL )
+ return DRVMGR_FAIL;
+
+ if ((status = gr_rasta_spw_router_hw_init(priv)) != 0) {
+ genirq_destroy(priv->genirq);
+ printf(" Failed to initialize GR-RASTA-SPW-ROUTER HW: %d\n", status);
+ return DRVMGR_FAIL;
+ }
+
+ /* Init amba bus */
+ priv->config.abus = &priv->abus;
+ priv->config.ops = &ambapp_rasta_spw_router_ops;
+ priv->config.maps_up = &priv->bus_maps_up[0];
+ priv->config.maps_down = &priv->bus_maps_down[0];
+ if ( priv->dev->minor_drv < gr_rasta_spw_router_resources_cnt ) {
+ priv->config.resources = gr_rasta_spw_router_resources[priv->dev->minor_drv];
+ } else {
+ priv->config.resources = NULL;
+ }
+
+ /* Create and register AMBA PnP bus. */
+ return ambapp_bus_register(dev, &priv->config);
+}
+
+int gr_rasta_spw_router_init2(struct drvmgr_dev *dev)
+{
+ struct gr_rasta_spw_router_priv *priv = dev->priv;
+
+ /* Clear any old interrupt requests */
+ drvmgr_interrupt_clear(dev, 0);
+
+ /* Enable System IRQ so that GR-RASTA-SPW-ROUTER PCI target interrupt
+ * goes through.
+ *
+ * It is important to enable it in stage init2. If interrupts were
+ * enabled in init1 this might hang the system when more than one
+ * PCI board is connected, this is because PCI interrupts might
+ * be shared and PCI board 2 have not initialized and
+ * might therefore drive interrupt already when entering init1().
+ */
+ drvmgr_interrupt_register(
+ dev,
+ 0,
+ "gr_rasta_spw_router",
+ gr_rasta_spw_router_isr,
+ (void *)priv);
+
+ return gr_rasta_spw_router_hw_init2(priv);
+}
+
+int ambapp_rasta_spw_router_int_register(
+ struct drvmgr_dev *dev,
+ int irq,
+ const char *info,
+ drvmgr_isr handler,
+ void *arg)
+{
+ struct gr_rasta_spw_router_priv *priv = dev->parent->dev->priv;
+ rtems_interrupt_level level;
+ int status;
+
+ rtems_interrupt_disable(level);
+
+ status = genirq_register(priv->genirq, irq, handler, arg);
+ if (status == 0) {
+ /* Clear IRQ for first registered handler */
+ priv->irq->iclear = (1<<irq);
+ } else if (status == 1)
+ status = 0;
+
+ if (status != 0) {
+ rtems_interrupt_enable(level);
+ return DRVMGR_FAIL;
+ }
+
+ status = genirq_enable(priv->genirq, irq, handler, arg);
+ if ( status == 0 ) {
+ /* Enable IRQ for first enabled handler only */
+ priv->irq->mask[0] |= (1<<irq); /* unmask interrupt source */
+ } else if ( status == 1 )
+ status = 0;
+
+ rtems_interrupt_enable(level);
+
+ return status;
+}
+
+int ambapp_rasta_spw_router_int_unregister(
+ struct drvmgr_dev *dev,
+ int irq,
+ drvmgr_isr isr,
+ void *arg)
+{
+ struct gr_rasta_spw_router_priv *priv = dev->parent->dev->priv;
+ rtems_interrupt_level level;
+ int status;
+
+ rtems_interrupt_disable(level);
+
+ status = genirq_disable(priv->genirq, irq, isr, arg);
+ if ( status == 0 ) {
+ /* Disable IRQ only when no enabled handler exists */
+ priv->irq->mask[0] &= ~(1<<irq); /* mask interrupt source */
+ }
+
+ status = genirq_unregister(priv->genirq, irq, isr, arg);
+ if ( status != 0 )
+ status = DRVMGR_FAIL;
+
+ rtems_interrupt_enable(level);
+
+ return status;
+}
+
+int ambapp_rasta_spw_router_int_unmask(
+ struct drvmgr_dev *dev,
+ int irq)
+{
+ struct gr_rasta_spw_router_priv *priv = dev->parent->dev->priv;
+ rtems_interrupt_level level;
+
+ DBG("RASTA-SPW-ROUTER IRQ %d: unmask\n", irq);
+
+ if ( genirq_check(priv->genirq, irq) )
+ return DRVMGR_EINVAL;
+
+ rtems_interrupt_disable(level);
+
+ /* Enable IRQ for first enabled handler only */
+ priv->irq->mask[0] |= (1<<irq); /* unmask interrupt source */
+
+ rtems_interrupt_enable(level);
+
+ return DRVMGR_OK;
+}
+
+int ambapp_rasta_spw_router_int_mask(
+ struct drvmgr_dev *dev,
+ int irq)
+{
+ struct gr_rasta_spw_router_priv *priv = dev->parent->dev->priv;
+ rtems_interrupt_level level;
+
+ DBG("RASTA-SPW-ROUTER IRQ %d: mask\n", irq);
+
+ if ( genirq_check(priv->genirq, irq) )
+ return DRVMGR_EINVAL;
+
+ rtems_interrupt_disable(level);
+
+ /* Disable/mask IRQ */
+ priv->irq->mask[0] &= ~(1<<irq); /* mask interrupt source */
+
+ rtems_interrupt_enable(level);
+
+ return DRVMGR_OK;
+}
+
+int ambapp_rasta_spw_router_int_clear(
+ struct drvmgr_dev *dev,
+ int irq)
+{
+ struct gr_rasta_spw_router_priv *priv = dev->parent->dev->priv;
+
+ if ( genirq_check(priv->genirq, irq) )
+ return DRVMGR_EINVAL;
+
+ priv->irq->iclear = (1<<irq);
+
+ return DRVMGR_OK;
+}
+
+int ambapp_rasta_spw_router_get_params(struct drvmgr_dev *dev, struct drvmgr_bus_params *params)
+{
+ struct gr_rasta_spw_router_priv *priv = dev->parent->dev->priv;
+
+ /* Device name prefix pointer, skip /dev */
+ params->dev_prefix = &priv->prefix[5];
+
+ return 0;
+}
+
+void gr_rasta_spw_router_print_dev(struct drvmgr_dev *dev, int options)
+{
+ struct gr_rasta_spw_router_priv *priv = dev->priv;
+ struct pci_dev_info *devinfo = priv->devinfo;
+ uint32_t bar0, bar0_size;
+
+ /* Print */
+ printf("--- GR-RASTA-SPW-ROUTER [bus 0x%x, dev 0x%x, fun 0x%x] ---\n",
+ PCI_DEV_EXPAND(priv->pcidev));
+
+ bar0 = devinfo->resources[0].address;
+ bar0_size = devinfo->resources[0].size;
+ printf(" PCI BAR[0]: 0x%lx - 0x%lx\n", bar0, bar0 + bar0_size - 1);
+ printf(" IRQ REGS: 0x%x\n", (unsigned int)priv->irq);
+ printf(" IRQ: %d\n", devinfo->irq);
+ printf(" PCI REVISION: %d\n", devinfo->rev);
+ printf(" FREQ: %d Hz\n", priv->version->amba_freq_hz);
+ printf(" IMASK: 0x%08x\n", priv->irq->mask[0]);
+ printf(" IPEND: 0x%08x\n", priv->irq->ipend);
+
+ /* Print amba config */
+ if (options & RASTA_SPW_ROUTER_OPTIONS_AMBA)
+ ambapp_print(&priv->abus, 10);
+
+#if 0
+ /* Print IRQ handlers and their arguments */
+ if (options & RASTA_SPW_ROUTER_OPTIONS_IRQ) {
+ int i;
+ for(i = 0; i < 16; i++) {
+ printf(" IRQ[%02d]: 0x%x, arg: 0x%x\n",
+ i, (unsigned int)priv->isrs[i].handler,
+ (unsigned int)priv->isrs[i].arg);
+ }
+ }
+#endif
+}
+
+void gr_rasta_spw_router_print(int options)
+{
+ struct pci_drv_info *drv = &gr_rasta_spw_router_info;
+ struct drvmgr_dev *dev;
+
+ dev = drv->general.dev;
+ while(dev) {
+ gr_rasta_spw_router_print_dev(dev, options);
+ dev = dev->next_in_drv;
+ }
+}
diff --git a/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_tmtc.c b/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_tmtc.c
new file mode 100644
index 0000000..7a10083
--- /dev/null
+++ b/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_tmtc.c
@@ -0,0 +1,684 @@
+/* GR-RASTA-TMTC PCI Target driver.
+ *
+ * COPYRIGHT (c) 2008.
+ * Cobham Gaisler AB.
+ *
+ * Configures the GR-RASTA-TMTC interface PCI board.
+ * This driver provides a AMBA PnP bus by using the general part
+ * of the AMBA PnP bus driver (ambapp_bus.c).
+ *
+ * Driver resources for the AMBA PnP bus provided can be set by overriding
+ * the defaults by declaring gr_rasta_tmtc_resources[].
+ *
+ * The license and distribution terms for this file may be
+ * found in found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+
+#include <bsp.h>
+#include <rtems/bspIo.h>
+#include <pci.h>
+
+#include <ambapp.h>
+#include <grlib.h>
+#include <drvmgr/drvmgr.h>
+#include <drvmgr/ambapp_bus.h>
+#include <drvmgr/pci_bus.h>
+#include <genirq.h>
+
+#include <gr_rasta_tmtc.h>
+
+/* Determines which PCI address the AHB masters will access, it should be
+ * set so that the masters can access the CPU RAM. Default is base of CPU RAM,
+ * CPU RAM is mapped 1:1 to PCI space.
+ */
+extern unsigned int _RAM_START;
+#define AHBMST2PCIADR (((unsigned int)&_RAM_START) & 0xf0000000)
+
+#define GAISLER_GPIO 0x01a
+#define AHB1_BASE_ADDR 0x80000000
+#define AHB1_IOAREA_BASE_ADDR 0x80200000
+
+/* #define DEBUG 1 */
+
+#ifdef DEBUG
+#define DBG(x...) printk(x)
+#else
+#define DBG(x...)
+#endif
+
+int gr_rasta_tmtc_init1(struct drvmgr_dev *dev);
+int gr_rasta_tmtc_init2(struct drvmgr_dev *dev);
+
+struct grpci_regs {
+ volatile unsigned int cfg_stat;
+ volatile unsigned int bar0;
+ volatile unsigned int page0;
+ volatile unsigned int bar1;
+ volatile unsigned int page1;
+ volatile unsigned int iomap;
+ volatile unsigned int stat_cmd;
+};
+
+struct gr_rasta_tmtc_ver {
+ const unsigned int amba_freq_hz; /* The frequency */
+ const unsigned int amba_ioarea; /* The address where the PnP IOAREA starts at */
+};
+
+/* Private data structure for driver */
+struct gr_rasta_tmtc_priv {
+ /* Driver management */
+ struct drvmgr_dev *dev;
+ char prefix[20];
+
+ /* PCI */
+ pci_dev_t pcidev;
+ struct pci_dev_info *devinfo;
+ uint32_t ahbmst2pci_map;
+
+ /* IRQ */
+ genirq_t genirq;
+
+ /* GR-RASTA-TMTC */
+ struct gr_rasta_tmtc_ver *version;
+ struct irqmp_regs *irq;
+ struct grpci_regs *grpci;
+ struct grgpio_regs *gpio;
+ struct drvmgr_map_entry bus_maps_down[3];
+ struct drvmgr_map_entry bus_maps_up[2];
+
+ /* AMBA Plug&Play information on GR-RASTA-TMTC */
+ struct ambapp_bus abus;
+ struct ambapp_mmap amba_maps[4];
+ struct ambapp_config config;
+};
+
+struct gr_rasta_tmtc_ver gr_rasta_tmtc_ver0 = {
+ .amba_freq_hz = 30000000,
+ .amba_ioarea = AHB1_IOAREA_BASE_ADDR,
+};
+
+int ambapp_rasta_tmtc_int_register(
+ struct drvmgr_dev *dev,
+ int irq,
+ const char *info,
+ drvmgr_isr handler,
+ void *arg);
+int ambapp_rasta_tmtc_int_unregister(
+ struct drvmgr_dev *dev,
+ int irq,
+ drvmgr_isr handler,
+ void *arg);
+int ambapp_rasta_tmtc_int_unmask(
+ struct drvmgr_dev *dev,
+ int irq);
+int ambapp_rasta_tmtc_int_mask(
+ struct drvmgr_dev *dev,
+ int irq);
+int ambapp_rasta_tmtc_int_clear(
+ struct drvmgr_dev *dev,
+ int irq);
+int ambapp_rasta_tmtc_get_params(
+ struct drvmgr_dev *dev,
+ struct drvmgr_bus_params *params);
+
+struct ambapp_ops ambapp_rasta_tmtc_ops = {
+ .int_register = ambapp_rasta_tmtc_int_register,
+ .int_unregister = ambapp_rasta_tmtc_int_unregister,
+ .int_unmask = ambapp_rasta_tmtc_int_unmask,
+ .int_mask = ambapp_rasta_tmtc_int_mask,
+ .int_clear = ambapp_rasta_tmtc_int_clear,
+ .get_params = ambapp_rasta_tmtc_get_params
+};
+
+struct drvmgr_drv_ops gr_rasta_tmtc_ops =
+{
+ .init = {gr_rasta_tmtc_init1, gr_rasta_tmtc_init2, NULL, NULL},
+ .remove = NULL,
+ .info = NULL,
+};
+
+struct pci_dev_id_match gr_rasta_tmtc_ids[] =
+{
+ PCIID_DEVVEND(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_RASTA_TMTC),
+ PCIID_END_TABLE /* Mark end of table */
+};
+
+struct pci_drv_info gr_rasta_tmtc_info =
+{
+ {
+ DRVMGR_OBJ_DRV, /* Driver */
+ NULL, /* Next driver */
+ NULL, /* Device list */
+ DRIVER_PCI_GAISLER_RASTATMTC_ID,/* Driver ID */
+ "GR-RASTA-TMTC_DRV", /* Driver Name */
+ DRVMGR_BUS_TYPE_PCI, /* Bus Type */
+ &gr_rasta_tmtc_ops,
+ NULL, /* Funcs */
+ 0, /* No devices yet */
+ sizeof(struct gr_rasta_tmtc_priv) /* Let drvmgr alloc private */
+ },
+ &gr_rasta_tmtc_ids[0]
+};
+
+/* Driver resources configuration for the AMBA bus on the GR-RASTA-TMTC board.
+ * It is declared weak so that the user may override it from the project file,
+ * if the default settings are not enough.
+ *
+ * The configuration consists of an array of configuration pointers, each
+ * pointer determine the configuration of one GR-RASTA-TMTC board. Pointer
+ * zero is for board0, pointer 1 for board1 and so on.
+ *
+ * The array must end with a NULL pointer.
+ */
+struct drvmgr_bus_res *gr_rasta_tmtc_resources[] __attribute__((weak)) =
+{
+ NULL,
+};
+int gr_rasta_tmtc_resources_cnt = 0;
+
+void gr_rasta_tmtc_register_drv(void)
+{
+ DBG("Registering GR-RASTA-TMTC PCI driver\n");
+ drvmgr_drv_register(&gr_rasta_tmtc_info.general);
+}
+
+void gr_rasta_tmtc_isr (void *arg)
+{
+ struct gr_rasta_tmtc_priv *priv = arg;
+ unsigned int status, tmp;
+ int irq;
+ tmp = status = priv->irq->ipend;
+
+ /* printk("GR-RASTA-TMTC: IRQ 0x%x\n",status); */
+
+ for(irq=0; irq<32; irq++) {
+ if ( status & (1<<irq) ) {
+ genirq_doirq(priv->genirq, irq);
+ priv->irq->iclear = (1<<irq);
+ status &= ~(1<<irq);
+ if ( status == 0 )
+ break;
+ }
+ }
+
+ /* ACK interrupt, this is because PCI is Level, so the IRQ Controller still drives the IRQ. */
+ if ( tmp )
+ drvmgr_interrupt_clear(priv->dev, 0);
+
+ DBG("RASTA-TMTC-IRQ: 0x%x\n", tmp);
+}
+
+int gr_rasta_tmtc_hw_init(struct gr_rasta_tmtc_priv *priv)
+{
+ unsigned int *page0 = NULL;
+ struct ambapp_dev *tmp;
+ struct ambapp_ahb_info *ahb;
+ unsigned int pci_freq_hz;
+ pci_dev_t pcidev = priv->pcidev;
+ struct pci_dev_info *devinfo = priv->devinfo;
+ uint32_t bar0, bar0_size;
+
+ /* Select version of GR-RASTA-TMTC board */
+ switch (devinfo->rev) {
+ case 0:
+ priv->version = &gr_rasta_tmtc_ver0;
+ break;
+ default:
+ return -2;
+ }
+
+ bar0 = devinfo->resources[0].address;
+ bar0_size = devinfo->resources[0].size;
+ page0 = (unsigned int *)(bar0 + bar0_size/2);
+
+ /* Point PAGE0 to start of Plug and Play information */
+ *page0 = priv->version->amba_ioarea & 0xf0000000;
+
+#if 0
+ {
+ uint32_t data;
+ /* set parity error response */
+ pci_cfg_r32(pcidev, PCI_COMMAND, &data);
+ pci_cfg_w32(pcidev, PCI_COMMAND, (data|PCI_COMMAND_PARITY));
+ }
+#endif
+
+ /* Scan AMBA Plug&Play */
+
+ /* AMBA MAP bar0 (in CPU) ==> 0x80000000(remote amba address) */
+ priv->amba_maps[0].size = 0x10000000;
+ priv->amba_maps[0].local_adr = bar0;
+ priv->amba_maps[0].remote_adr = AHB1_BASE_ADDR;
+
+ /* AMBA MAP bar1 (in CPU) ==> 0x40000000(remote amba address) */
+ priv->amba_maps[1].size = devinfo->resources[1].size;
+ priv->amba_maps[1].local_adr = devinfo->resources[1].address;
+ priv->amba_maps[1].remote_adr = 0x40000000;
+
+ /* Addresses not matching with map be untouched */
+ priv->amba_maps[2].size = 0xfffffff0;
+ priv->amba_maps[2].local_adr = 0;
+ priv->amba_maps[2].remote_adr = 0;
+
+ /* Mark end of table */
+ priv->amba_maps[3].size=0;
+ priv->amba_maps[3].local_adr = 0;
+ priv->amba_maps[3].remote_adr = 0;
+
+ /* Start AMBA PnP scan at first AHB bus */
+ ambapp_scan(&priv->abus,
+ bar0 + (priv->version->amba_ioarea & ~0xf0000000),
+ NULL, &priv->amba_maps[0]);
+
+ /* Frequency is the same as the PCI bus frequency */
+ drvmgr_freq_get(priv->dev, 0, &pci_freq_hz);
+
+ /* Initialize Frequency of AMBA bus */
+ ambapp_freq_init(&priv->abus, NULL, pci_freq_hz);
+
+ /* Point PAGE0 to start of APB area */
+ *page0 = AHB1_BASE_ADDR;
+
+ /* Find GRPCI controller */
+ tmp = (void *)ambapp_for_each(&priv->abus,
+ (OPTIONS_ALL|OPTIONS_APB_SLVS),
+ VENDOR_GAISLER, GAISLER_PCIFBRG,
+ ambapp_find_by_idx, NULL);
+ if ( !tmp ) {
+ return -3;
+ }
+ priv->grpci = (struct grpci_regs *)((struct ambapp_apb_info *)tmp->devinfo)->start;
+
+ /* Set GRPCI mmap so that AMBA masters can access CPU-RAM over
+ * the PCI window.
+ */
+ priv->grpci->cfg_stat = (priv->grpci->cfg_stat & 0x0fffffff) |
+ (priv->ahbmst2pci_map & 0xf0000000);
+ priv->grpci->page1 = 0x40000000;
+
+ /* Find IRQ controller, Clear all current IRQs */
+ tmp = (void *)ambapp_for_each(&priv->abus,
+ (OPTIONS_ALL|OPTIONS_APB_SLVS),
+ VENDOR_GAISLER, GAISLER_IRQMP,
+ ambapp_find_by_idx, NULL);
+ if ( !tmp ) {
+ return -4;
+ }
+ priv->irq = (struct irqmp_regs *)DEV_TO_APB(tmp)->start;
+ /* Set up GR-RASTA-TMTC irq controller */
+ priv->irq->mask[0] = 0;
+ priv->irq->iclear = 0xffffffff;
+ priv->irq->ilevel = 0;
+
+ /* Find First GPIO controller */
+ tmp = (void *)ambapp_for_each(&priv->abus,
+ (OPTIONS_ALL|OPTIONS_APB_SLVS),
+ VENDOR_GAISLER, GAISLER_GPIO,
+ ambapp_find_by_idx, NULL);
+ if ( !tmp ) {
+ return -5;
+ }
+ priv->gpio = (struct grgpio_regs *) (((struct ambapp_apb_info *)tmp->devinfo)->start);
+ /* Clear GR-RASTA-TMTC GPIO controller */
+ priv->gpio->imask = 0;
+ priv->gpio->ipol = 0;
+ priv->gpio->iedge = 0;
+ priv->gpio->bypass = 0;
+ /* Set up GR-RASTA-TMTC GPIO controller to select GRTM and GRTC */
+ priv->gpio->output = (GR_TMTC_GPIO_GRTM_SEL|GR_TMTC_GPIO_TRANSP_CLK) | (GR_TMTC_GPIO_TC_BIT_LOCK|GR_TMTC_GPIO_TC_RF_AVAIL|GR_TMTC_GPIO_TC_ACTIVE_HIGH|GR_TMTC_GPIO_TC_RISING_CLK);
+ priv->gpio->dir = 0xffffffff;
+ DBG("GR-TMTC GPIO: 0x%x\n", (unsigned int)priv->gpio);
+
+ /* Enable DMA by enabling PCI target as master */
+ pci_master_enable(pcidev);
+
+ /* DOWN streams translation table */
+ priv->bus_maps_down[0].name = "PCI BAR0 -> AMBA";
+ priv->bus_maps_down[0].size = priv->amba_maps[0].size;
+ priv->bus_maps_down[0].from_adr = (void *)priv->amba_maps[0].local_adr;
+ priv->bus_maps_down[0].to_adr = (void *)priv->amba_maps[0].remote_adr;
+
+ priv->bus_maps_down[1].name = "PCI BAR1 -> AMBA";
+ priv->bus_maps_down[1].size = priv->amba_maps[1].size;
+ priv->bus_maps_down[1].from_adr = (void *)priv->amba_maps[1].local_adr;
+ priv->bus_maps_down[1].to_adr = (void *)priv->amba_maps[1].remote_adr;
+
+ /* Mark end of translation table */
+ priv->bus_maps_down[2].size = 0;
+
+ /* Find GRPCI controller AHB Slave interface */
+ tmp = (struct ambapp_dev *)ambapp_for_each(&priv->abus,
+ (OPTIONS_ALL|OPTIONS_AHB_SLVS),
+ VENDOR_GAISLER, GAISLER_PCIFBRG,
+ ambapp_find_by_idx, NULL);
+ if ( !tmp ) {
+ return -6;
+ }
+ ahb = (struct ambapp_ahb_info *)tmp->devinfo;
+
+ /* UP streams translation table */
+ priv->bus_maps_up[0].name = "AMBA GRPCI Window";
+ priv->bus_maps_up[0].size = ahb->mask[0]; /* AMBA->PCI Window on GR-RASTA-TMTC board */
+ priv->bus_maps_up[0].from_adr = (void *)ahb->start[0];
+ priv->bus_maps_up[0].to_adr = (void *)
+ (priv->ahbmst2pci_map & 0xf0000000);
+
+ /* Mark end of translation table */
+ priv->bus_maps_up[1].size = 0;
+
+ /* Successfully registered the RASTA board */
+ return 0;
+}
+
+void gr_rasta_tmtc_hw_init2(struct gr_rasta_tmtc_priv *priv)
+{
+ /* Enable DMA by enabling PCI target as master */
+ pci_master_enable(priv->pcidev);
+}
+
+/* Called when a PCI target is found with the PCI device and vendor ID
+ * given in gr_rasta_tmtc_ids[].
+ */
+int gr_rasta_tmtc_init1(struct drvmgr_dev *dev)
+{
+ struct gr_rasta_tmtc_priv *priv;
+ struct pci_dev_info *devinfo;
+ int status;
+ uint32_t bar0, bar1, bar0_size, bar1_size;
+ union drvmgr_key_value *value;
+
+ priv = dev->priv;
+ if (!priv)
+ return DRVMGR_NOMEM;
+ priv->dev = dev;
+
+ /* Determine number of configurations */
+ if ( gr_rasta_tmtc_resources_cnt == 0 ) {
+ while ( gr_rasta_tmtc_resources[gr_rasta_tmtc_resources_cnt] )
+ gr_rasta_tmtc_resources_cnt++;
+ }
+
+ /* Generate Device prefix */
+
+ strcpy(priv->prefix, "/dev/rastatmtc0");
+ priv->prefix[14] += dev->minor_drv;
+ mkdir(priv->prefix, S_IRWXU | S_IRWXG | S_IRWXO);
+ priv->prefix[15] = '/';
+ priv->prefix[16] = '\0';
+
+ priv->devinfo = devinfo = (struct pci_dev_info *)dev->businfo;
+ priv->pcidev = devinfo->pcidev;
+ bar0 = devinfo->resources[0].address;
+ bar0_size = devinfo->resources[0].size;
+ bar1 = devinfo->resources[1].address;
+ bar1_size = devinfo->resources[1].size;
+ printf("\n\n--- GR-RASTA-TMTC[%d] ---\n", dev->minor_drv);
+ printf(" PCI BUS: 0x%x, SLOT: 0x%x, FUNCTION: 0x%x\n",
+ PCI_DEV_EXPAND(priv->pcidev));
+ printf(" PCI VENDOR: 0x%04x, DEVICE: 0x%04x\n",
+ devinfo->id.vendor, devinfo->id.device);
+ printf(" PCI BAR[0]: 0x%lx - 0x%lx\n", bar0, bar0 + bar0_size - 1);
+ printf(" PCI BAR[1]: 0x%lx - 0x%lx\n", bar1, bar1 + bar1_size - 1);
+ printf(" IRQ: %d\n\n\n", devinfo->irq);
+
+ /* all neccessary space assigned to GR-RASTA-IO target? */
+ if ((bar0_size == 0) || (bar1_size == 0))
+ return DRVMGR_ENORES;
+
+ /* Let user override which PCI address the AHB masters of the
+ * GR-RASTA-TMTC board access when doing DMA to CPU RAM. The AHB masters
+ * access the PCI Window of the AMBA bus, the MSB 4-bits of that address
+ * is translated according this config option before the address
+ * goes out on the PCI bus.
+ * Only the 4 MSB bits have an effect;
+ */
+ value = drvmgr_dev_key_get(priv->dev, "ahbmst2pci", KEY_TYPE_INT);
+ if (value)
+ priv->ahbmst2pci_map = value->i;
+ else
+ priv->ahbmst2pci_map = AHBMST2PCIADR; /* default */
+
+ priv->genirq = genirq_init(32);
+ if ( priv->genirq == NULL )
+ return DRVMGR_FAIL;
+
+ status = gr_rasta_tmtc_hw_init(priv);
+ if ( status != 0 ) {
+ genirq_destroy(priv->genirq);
+ printf(" Failed to initialize GR-RASTA-TMTC HW: %d\n", status);
+ return DRVMGR_FAIL;
+ }
+
+ /* Init amba bus */
+ priv->config.abus = &priv->abus;
+ priv->config.ops = &ambapp_rasta_tmtc_ops;
+ priv->config.maps_up = &priv->bus_maps_up[0];
+ priv->config.maps_down = &priv->bus_maps_down[0];
+ if ( priv->dev->minor_drv < gr_rasta_tmtc_resources_cnt ) {
+ priv->config.resources = gr_rasta_tmtc_resources[priv->dev->minor_drv];
+ } else {
+ priv->config.resources = NULL;
+ }
+
+ return ambapp_bus_register(dev, &priv->config);
+}
+
+int gr_rasta_tmtc_init2(struct drvmgr_dev *dev)
+{
+ struct gr_rasta_tmtc_priv *priv = dev->priv;
+
+ /* Clear any old interrupt requests */
+ drvmgr_interrupt_clear(priv->dev, 0);
+
+ /* Enable System IRQ so that GR-RASTA-TMTC PCI target interrupt goes
+ * through.
+ *
+ * It is important to enable it in stage init2. If interrupts were
+ * enabled in init1 this might hang the system when more than one
+ * PCI target is connected, this is because PCI interrupts might
+ * be shared and PCI board 2 have not initialized and
+ * might therefore drive interrupt already when entering init1().
+ */
+ drvmgr_interrupt_register(
+ priv->dev,
+ 0,
+ "gr_rasta_tmtc",
+ gr_rasta_tmtc_isr,
+ (void *)priv);
+
+ gr_rasta_tmtc_hw_init2(priv);
+
+ return DRVMGR_OK;
+}
+
+int ambapp_rasta_tmtc_int_register(
+ struct drvmgr_dev *dev,
+ int irq,
+ const char *info,
+ drvmgr_isr handler,
+ void *arg)
+{
+ struct gr_rasta_tmtc_priv *priv = dev->parent->dev->priv;
+ rtems_interrupt_level level;
+ int status;
+
+ rtems_interrupt_disable(level);
+
+ status = genirq_register(priv->genirq, irq, handler, arg);
+ if ( status == 0 ) {
+ /* Disable and clear IRQ for first registered handler */
+ priv->irq->iclear = (1<<irq);
+ } else if ( status == 1 )
+ status = 0;
+
+ if (status != 0) {
+ rtems_interrupt_enable(level);
+ return DRVMGR_FAIL;
+ }
+
+ status = genirq_enable(priv->genirq, irq, handler, arg);
+ if ( status == 0 ) {
+ /* Enable IRQ for first enabled handler only */
+ priv->irq->mask[0] |= (1<<irq); /* unmask interrupt source */
+ } else if ( status == 1 )
+ status = 0;
+
+ rtems_interrupt_enable(level);
+
+ return status;
+}
+
+int ambapp_rasta_tmtc_int_unregister(
+ struct drvmgr_dev *dev,
+ int irq,
+ drvmgr_isr isr,
+ void *arg)
+{
+ struct gr_rasta_tmtc_priv *priv = dev->parent->dev->priv;
+ rtems_interrupt_level level;
+ int status;
+
+ rtems_interrupt_disable(level);
+
+ status = genirq_disable(priv->genirq, irq, isr, arg);
+ if ( status == 0 ) {
+ /* Disable IRQ only when no enabled handler exists */
+ priv->irq->mask[0] &= ~(1<<irq); /* mask interrupt source */
+ } else if ( status == 1 )
+ status = 0;
+
+ status = genirq_unregister(priv->genirq, irq, isr, arg);
+ if ( status != 0 )
+ status = DRVMGR_FAIL;
+
+ rtems_interrupt_enable(level);
+
+ return status;
+}
+
+int ambapp_rasta_tmtc_int_unmask(
+ struct drvmgr_dev *dev,
+ int irq)
+{
+ struct gr_rasta_tmtc_priv *priv = dev->parent->dev->priv;
+ rtems_interrupt_level level;
+
+ DBG("RASTA-TMTC IRQ %d: unmask\n", irq);
+
+ if ( genirq_check(priv->genirq, irq) )
+ return DRVMGR_EINVAL;
+
+ rtems_interrupt_disable(level);
+
+ /* Enable IRQ */
+ priv->irq->mask[0] |= (1<<irq); /* unmask interrupt source */
+
+ rtems_interrupt_enable(level);
+
+ return DRVMGR_OK;
+}
+
+int ambapp_rasta_tmtc_int_mask(
+ struct drvmgr_dev *dev,
+ int irq)
+{
+ struct gr_rasta_tmtc_priv *priv = dev->parent->dev->priv;
+ rtems_interrupt_level level;
+
+ DBG("RASTA-TMTC IRQ %d: mask\n", irq);
+
+ if ( genirq_check(priv->genirq, irq) )
+ return DRVMGR_EINVAL;
+
+ rtems_interrupt_disable(level);
+
+ /* Disable IRQ */
+ priv->irq->mask[0] &= ~(1<<irq); /* mask interrupt source */
+
+ rtems_interrupt_enable(level);
+
+ return DRVMGR_OK;
+}
+
+int ambapp_rasta_tmtc_int_clear(
+ struct drvmgr_dev *dev,
+ int irq)
+{
+ struct gr_rasta_tmtc_priv *priv = dev->parent->dev->priv;
+
+ if ( genirq_check(priv->genirq, irq) )
+ return DRVMGR_FAIL;
+
+ priv->irq->iclear = (1<<irq);
+
+ return DRVMGR_OK;
+}
+
+int ambapp_rasta_tmtc_get_params(struct drvmgr_dev *dev, struct drvmgr_bus_params *params)
+{
+ struct gr_rasta_tmtc_priv *priv = dev->parent->dev->priv;
+
+ /* Device name prefix pointer, skip /dev */
+ params->dev_prefix = &priv->prefix[5];
+
+ return 0;
+}
+
+void gr_rasta_tmtc_print_dev(struct drvmgr_dev *dev, int options)
+{
+ struct gr_rasta_tmtc_priv *priv = dev->priv;
+ struct pci_dev_info *devinfo = priv->devinfo;
+ uint32_t bar0, bar1, bar0_size, bar1_size;
+
+ /* Print */
+ printf("--- GR-RASTA-TMTC [bus 0x%x, dev 0x%x, fun 0x%x] ---\n",
+ PCI_DEV_EXPAND(priv->pcidev));
+
+ bar0 = devinfo->resources[0].address;
+ bar0_size = devinfo->resources[0].size;
+ bar1 = devinfo->resources[1].address;
+ bar1_size = devinfo->resources[1].size;
+
+ printf(" PCI BAR[0]: 0x%lx - 0x%lx\n", bar0, bar0 + bar0_size - 1);
+ printf(" PCI BAR[1]: 0x%lx - 0x%lx\n", bar1, bar1 + bar1_size - 1);
+ printf(" IRQ: %d\n", devinfo->irq);
+ printf(" PCI REVISION: %d\n", devinfo->rev);
+ printf(" FREQ: %d Hz\n", priv->version->amba_freq_hz);
+ printf(" IMASK: 0x%08x\n", priv->irq->mask[0]);
+ printf(" IPEND: 0x%08x\n", priv->irq->ipend);
+
+ /* Print amba config */
+ if ( options & RASTA_TMTC_OPTIONS_AMBA ) {
+ ambapp_print(&priv->abus, 10);
+ }
+
+#if 0
+ /* Print IRQ handlers and their arguments */
+ if ( options & RASTA_TMTC_OPTIONS_IRQ ) {
+ int i;
+ for(i=0; i<16; i++) {
+ printf(" IRQ[%02d]: 0x%x, arg: 0x%x\n",
+ i, (unsigned int)priv->isrs[i].handler, (unsigned int)priv->isrs[i].arg);
+ }
+ }
+#endif
+}
+
+void gr_rasta_tmtc_print(int options)
+{
+ struct pci_drv_info *drv = &gr_rasta_tmtc_info;
+ struct drvmgr_dev *dev;
+
+ dev = drv->general.dev;
+ while(dev) {
+ gr_rasta_tmtc_print_dev(dev, options);
+ dev = dev->next_in_drv;
+ }
+}
diff --git a/c/src/lib/libbsp/sparc/shared/pci/gr_tmtc_1553.c b/c/src/lib/libbsp/sparc/shared/pci/gr_tmtc_1553.c
new file mode 100644
index 0000000..6b512a9
--- /dev/null
+++ b/c/src/lib/libbsp/sparc/shared/pci/gr_tmtc_1553.c
@@ -0,0 +1,571 @@
+/* GR-TMTC-1553 PCI Target driver.
+ *
+ * COPYRIGHT (c) 2008.
+ * Cobham Gaisler AB.
+ *
+ * Configures the GR-TMTC-1553 interface PCI board.
+ * This driver provides a AMBA PnP bus by using the general part
+ * of the AMBA PnP bus driver (ambapp_bus.c).
+ *
+ * Driver resources for the AMBA PnP bus provided can be set using
+ * gr_tmtc_1553_set_resources().
+ *
+ * The license and distribution terms for this file may be
+ * found in found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+
+#include <bsp.h>
+#include <rtems/bspIo.h>
+#include <pci.h>
+#include <pci/access.h>
+
+#include <ambapp.h>
+#include <grlib.h>
+#include <drvmgr/drvmgr.h>
+#include <drvmgr/ambapp_bus.h>
+#include <drvmgr/pci_bus.h>
+#include <genirq.h>
+
+#include <gr_tmtc_1553.h>
+
+
+/*#define DEBUG 1 */
+
+#ifdef DEBUG
+#define DBG(x...) printk(x)
+#else
+#define DBG(x...)
+#endif
+
+/* PCI ID */
+#define PCIID_VENDOR_GAISLER 0x1AC8
+
+int gr_tmtc_1553_init1(struct drvmgr_dev *dev);
+int gr_tmtc_1553_init2(struct drvmgr_dev *dev);
+
+struct gr_tmtc_1553_ver {
+ const unsigned int amba_freq_hz; /* The frequency */
+ const unsigned int amba_ioarea; /* The address where the PnP IOAREA starts at */
+};
+
+/* Private data structure for driver */
+struct gr_tmtc_1553_priv {
+ /* Driver management */
+ struct drvmgr_dev *dev;
+ char prefix[32];
+
+ /* PCI */
+ pci_dev_t pcidev;
+ struct pci_dev_info *devinfo;
+
+ /* IRQ */
+ genirq_t genirq;
+
+ struct gr_tmtc_1553_ver *version;
+ struct irqmp_regs *irq;
+ struct drvmgr_map_entry bus_maps_down[2];
+
+ struct ambapp_bus abus;
+ struct ambapp_mmap amba_maps[4];
+ struct ambapp_config config;
+};
+
+struct gr_tmtc_1553_ver gr_tmtc_1553_ver0 = {
+ .amba_freq_hz = 33333333,
+ .amba_ioarea = 0xfff00000,
+};
+
+
+int ambapp_tmtc_1553_int_register(
+ struct drvmgr_dev *dev,
+ int irq,
+ const char *info,
+ drvmgr_isr handler,
+ void *arg);
+int ambapp_tmtc_1553_int_unregister(
+ struct drvmgr_dev *dev,
+ int irq,
+ drvmgr_isr handler,
+ void *arg);
+int ambapp_tmtc_1553_int_unmask(
+ struct drvmgr_dev *dev,
+ int irq);
+int ambapp_tmtc_1553_int_mask(
+ struct drvmgr_dev *dev,
+ int irq);
+int ambapp_tmtc_1553_int_clear(
+ struct drvmgr_dev *dev,
+ int irq);
+int ambapp_tmtc_1553_get_params(
+ struct drvmgr_dev *dev,
+ struct drvmgr_bus_params *params);
+
+struct ambapp_ops ambapp_tmtc_1553_ops = {
+ .int_register = ambapp_tmtc_1553_int_register,
+ .int_unregister = ambapp_tmtc_1553_int_unregister,
+ .int_unmask = ambapp_tmtc_1553_int_unmask,
+ .int_mask = ambapp_tmtc_1553_int_mask,
+ .int_clear = ambapp_tmtc_1553_int_clear,
+ .get_params = ambapp_tmtc_1553_get_params
+};
+
+struct drvmgr_drv_ops gr_tmtc_1553_ops =
+{
+ {gr_tmtc_1553_init1, gr_tmtc_1553_init2, NULL, NULL},
+ NULL,
+ NULL
+};
+
+struct pci_dev_id_match gr_tmtc_1553_ids[] =
+{
+ PCIID_DEVVEND(PCIID_VENDOR_GAISLER, PCIID_DEVICE_GR_TMTC_1553),
+ PCIID_END_TABLE /* Mark end of table */
+};
+
+struct pci_drv_info gr_tmtc_1553_info =
+{
+ {
+ DRVMGR_OBJ_DRV, /* Driver */
+ NULL, /* Next driver */
+ NULL, /* Device list */
+ DRIVER_PCI_GAISLER_TMTC_1553_ID, /* Driver ID */
+ "GR-TMTC-1553_DRV", /* Driver Name */
+ DRVMGR_BUS_TYPE_PCI, /* Bus Type */
+ &gr_tmtc_1553_ops,
+ NULL, /* Funcs */
+ 0, /* No devices yet */
+ 0,
+ },
+ &gr_tmtc_1553_ids[0]
+};
+
+/* Driver resources configuration for the AMBA bus on the GR-RASTA-IO board.
+ * It is declared weak so that the user may override it from the project file,
+ * if the default settings are not enough.
+ *
+ * The configuration consists of an array of configuration pointers, each
+ * pointer determine the configuration of one GR-RASTA-IO board. Pointer
+ * zero is for board0, pointer 1 for board1 and so on.
+ *
+ * The array must end with a NULL pointer.
+ */
+struct drvmgr_bus_res *gr_tmtc_1553_resources[] __attribute__((weak)) =
+{
+ NULL
+};
+int gr_tmtc_1553_resources_cnt = 0;
+
+void gr_tmtc_1553_register_drv(void)
+{
+ DBG("Registering GR-TMTC-1553 PCI driver\n");
+ drvmgr_drv_register(&gr_tmtc_1553_info.general);
+}
+
+void gr_tmtc_1553_isr (void *arg)
+{
+ struct gr_tmtc_1553_priv *priv = arg;
+ unsigned int status, tmp;
+ int irq;
+ tmp = status = priv->irq->ipend;
+
+ /* DBG("GR-RASTA-IO: IRQ 0x%x\n",status); */
+
+ for(irq=0; irq<16; irq++) {
+ if ( status & (1<<irq) ) {
+ genirq_doirq(priv->genirq, irq);
+ priv->irq->iclear = (1<<irq);
+ status &= ~(1<<irq);
+ if ( status == 0 )
+ break;
+ }
+ }
+
+ /* ACK interrupt, this is because PCI is Level, so the IRQ Controller still drives the IRQ. */
+ if ( tmp )
+ drvmgr_interrupt_clear(priv->dev, 0);
+
+ DBG("GR-TMTC-1553-IRQ: 0x%x\n", tmp);
+}
+
+int gr_tmtc_1553_hw_init(struct gr_tmtc_1553_priv *priv)
+{
+ unsigned int *page0 = NULL;
+ struct ambapp_dev *tmp;
+ int status;
+ unsigned int pci_freq_hz;
+ struct pci_dev_info *devinfo = priv->devinfo;
+ uint32_t bar0, bar0_size;
+
+ /* Select version of GR-TMTC-1553 board */
+ switch (devinfo->rev) {
+ case 0:
+ priv->version = &gr_tmtc_1553_ver0;
+ break;
+ default:
+ return -2;
+ }
+
+ bar0 = devinfo->resources[0].address;
+ bar0_size = devinfo->resources[0].size;
+ page0 = (unsigned int *)(bar0 + bar0_size/2);
+
+ /* Point PAGE0 to start of board address map. RAM at 0xff000000, APB at 0xffc00000, IOAREA at 0xfff000000 */
+ /* XXX We assume little endian host with byte twisting enabled here */
+ *page0 = 0x010000ff; /* Set little endian mode on peripheral. */
+
+ /* Scan AMBA Plug&Play */
+
+ /* AMBA MAP bar0 (in CPU) ==> 0x80000000(remote amba address) */
+ priv->amba_maps[0].size = 0x1000000;
+ priv->amba_maps[0].local_adr = bar0;
+ priv->amba_maps[0].remote_adr = 0xff000000;
+
+ /* Addresses not matching with map be untouched */
+ priv->amba_maps[2].size = 0xfffffff0;
+ priv->amba_maps[2].local_adr = 0;
+ priv->amba_maps[2].remote_adr = 0;
+
+ /* Mark end of table */
+ priv->amba_maps[3].size=0;
+ priv->amba_maps[3].local_adr = 0;
+ priv->amba_maps[3].remote_adr = 0;
+
+ /* Start AMBA PnP scan at first AHB bus */
+ ambapp_scan(&priv->abus,
+ bar0 + (priv->version->amba_ioarea & ~0xff000000),
+ NULL, &priv->amba_maps[0]);
+
+ /* Frequency is the hsame as the PCI bus frequency */
+ drvmgr_freq_get(priv->dev, NULL, &pci_freq_hz);
+
+ ambapp_freq_init(&priv->abus, NULL, pci_freq_hz);
+
+ /* Find IRQ controller */
+ tmp = (void *)ambapp_for_each(&priv->abus,
+ (OPTIONS_ALL|OPTIONS_APB_SLVS),
+ VENDOR_GAISLER, GAISLER_IRQMP,
+ ambapp_find_by_idx, NULL);
+ if ( !tmp ) {
+ return -4;
+ }
+ priv->irq = (struct irqmp_regs *)DEV_TO_APB(tmp)->start;
+ /* Set up irq controller */
+ priv->irq->mask[0] = 0;
+ priv->irq->iclear = 0xffff;
+ priv->irq->ilevel = 0;
+
+ /* DOWN streams translation table */
+ priv->bus_maps_down[0].name = "PCI BAR0 -> AMBA";
+ priv->bus_maps_down[0].size = priv->amba_maps[0].size;
+ priv->bus_maps_down[0].from_adr = (void *)priv->amba_maps[0].local_adr;
+ priv->bus_maps_down[0].to_adr = (void *)priv->amba_maps[0].remote_adr;
+ /* Mark end of translation table */
+ priv->bus_maps_down[1].size = 0;
+
+ /* Successfully registered the board */
+ return 0;
+}
+
+
+/* Called when a PCI target is found with the PCI device and vendor ID
+ * given in gr_tmtc_1553_ids[].
+ */
+int gr_tmtc_1553_init1(struct drvmgr_dev *dev)
+{
+ struct gr_tmtc_1553_priv *priv;
+ struct pci_dev_info *devinfo;
+ int status;
+ uint32_t bar0, bar0_size;
+
+ /* PCI device does not have the IRQ line register, when PCI autoconf configures it the configuration
+ * is forgotten. We take the IRQ number from the PCI Host device (AMBA device), this works as long
+ * as PCI-IRQs are ored together on the bus.
+ *
+ * Note that this only works on LEON.
+ */
+ ((struct pci_dev_info *)dev->businfo)->irq = ((struct amba_dev_info *)dev->parent->dev->businfo)->info.irq;
+
+ priv = malloc(sizeof(struct gr_tmtc_1553_priv));
+ if ( !priv )
+ return DRVMGR_NOMEM;
+
+ memset(priv, 0, sizeof(*priv));
+ dev->priv = priv;
+ priv->dev = dev;
+
+ /* Determine number of configurations */
+ if ( gr_tmtc_1553_resources_cnt == 0 ) {
+ while ( gr_tmtc_1553_resources[gr_tmtc_1553_resources_cnt] )
+ gr_tmtc_1553_resources_cnt++;
+ }
+
+ /* Generate Device prefix */
+
+ strcpy(priv->prefix, "/dev/tmtc1553_0/");
+ priv->prefix[19] += dev->minor_drv;
+ mkdir(priv->prefix, S_IRWXU | S_IRWXG | S_IRWXO);
+ priv->prefix[20] = '/';
+ priv->prefix[21] = '\0';
+
+ priv->devinfo = devinfo = (struct pci_dev_info *)dev->businfo;
+ priv->pcidev = devinfo->pcidev;
+ bar0 = devinfo->resources[0].address;
+ bar0_size = devinfo->resources[0].size;
+ printf("\n\n--- GR-TMTC-1553[%d] ---\n", dev->minor_drv);
+ printf(" PCI BUS: 0x%x, SLOT: 0x%x, FUNCTION: 0x%x\n",
+ PCI_DEV_EXPAND(priv->pcidev));
+ printf(" PCI VENDOR: 0x%04x, DEVICE: 0x%04x\n",
+ devinfo->id.vendor, devinfo->id.device);
+ printf(" PCI BAR[0]: 0x%lx - 0x%lx\n", bar0, bar0 + bar0_size - 1);
+ printf(" IRQ: %d\n\n\n", devinfo->irq);
+
+ /* all neccessary space assigned to GR-TMTC-1553 target? */
+ if (bar0_size == 0)
+ return DRVMGR_ENORES;
+
+ priv->genirq = genirq_init(16);
+ if ( priv->genirq == NULL ) {
+ free(priv);
+ dev->priv = NULL;
+ return DRVMGR_FAIL;
+ }
+
+ status = gr_tmtc_1553_hw_init(priv);
+ if ( status != 0 ) {
+ genirq_destroy(priv->genirq);
+ free(priv);
+ dev->priv = NULL;
+ printf(" Failed to initialize GR-TMTC-1553 HW: %d\n", status);
+ return DRVMGR_FAIL;
+ }
+
+ /* Init amba bus */
+ priv->config.abus = &priv->abus;
+ priv->config.ops = &ambapp_tmtc_1553_ops;
+ priv->config.maps_down = &priv->bus_maps_down[0];
+ /* This PCI device has only target interface so DMA is not supported,
+ * which means that translation from AMBA->PCI should fail if attempted.
+ */
+ priv->config.maps_up = DRVMGR_TRANSLATE_NO_BRIDGE;
+ if ( priv->dev->minor_drv < gr_tmtc_1553_resources_cnt ) {
+ priv->config.resources = gr_tmtc_1553_resources[priv->dev->minor_drv];
+ } else {
+ priv->config.resources = NULL;
+ }
+
+ /* Create And Register AMBA PnP Bus */
+ return ambapp_bus_register(dev, &priv->config);
+}
+
+int gr_tmtc_1553_init2(struct drvmgr_dev *dev)
+{
+ struct gr_tmtc_1553_priv *priv = dev->priv;
+
+ /* Clear any old interrupt requests */
+ drvmgr_interrupt_clear(dev, 0);
+
+ /* Enable System IRQ so that GR-TMTC-1553 PCI target interrupt goes through.
+ *
+ * It is important to enable it in stage init2. If interrupts were enabled in init1
+ * this might hang the system when more than one PCI target is connected, this is
+ * because PCI interrupts might be shared and PCI target 2 have not initialized and
+ * might therefore drive interrupt already when entering init1().
+ */
+ drvmgr_interrupt_register(
+ dev,
+ 0,
+ "gr_tmtc_1553",
+ gr_tmtc_1553_isr,
+ (void *)priv);
+
+ return DRVMGR_OK;
+}
+
+int ambapp_tmtc_1553_int_register(
+ struct drvmgr_dev *dev,
+ int irq,
+ const char *info,
+ drvmgr_isr handler,
+ void *arg)
+{
+ struct gr_tmtc_1553_priv *priv = dev->parent->dev->priv;
+ rtems_interrupt_level level;
+ int status;
+
+ rtems_interrupt_disable(level);
+
+ status = genirq_register(priv->genirq, irq, handler, arg);
+ if ( status == 0 ) {
+ /* Disable and clear IRQ for first registered handler */
+ priv->irq->iclear = (1<<irq);
+ priv->irq->mask[0] &= ~(1<<irq); /* mask interrupt source */
+ } else if ( status == 1 )
+ status = 0;
+
+ if (status != 0) {
+ rtems_interrupt_enable(level);
+ return DRVMGR_FAIL;
+ }
+
+ status = genirq_enable(priv->genirq, irq, handler, arg);
+ if ( status == 0 ) {
+ /* Enable IRQ for first enabled handler only */
+ priv->irq->mask[0] |= (1<<irq); /* unmask interrupt source */
+ } else if ( status == 1 )
+ status = 0;
+
+ rtems_interrupt_enable(level);
+
+ return status;
+}
+
+int ambapp_tmtc_1553_int_unregister(
+ struct drvmgr_dev *dev,
+ int irq,
+ drvmgr_isr isr,
+ void *arg)
+{
+ struct gr_tmtc_1553_priv *priv = dev->parent->dev->priv;
+ rtems_interrupt_level level;
+ int status;
+
+ rtems_interrupt_disable(level);
+
+ status = genirq_disable(priv->genirq, irq, isr, arg);
+ if ( status == 0 ) {
+ /* Disable IRQ only when no enabled handler exists */
+ priv->irq->mask[0] &= ~(1<<irq); /* mask interrupt source */
+ } else if ( status == 1 )
+ status = 0;
+
+ status = genirq_unregister(priv->genirq, irq, isr, arg);
+ if ( status != 0 )
+ status = DRVMGR_FAIL;
+
+ rtems_interrupt_enable(level);
+
+ return status;
+}
+
+int ambapp_tmtc_1553_int_unmask(
+ struct drvmgr_dev *dev,
+ int irq)
+{
+ struct gr_tmtc_1553_priv *priv = dev->parent->dev->priv;
+ rtems_interrupt_level level;
+
+ DBG("TMTC-1553 IRQ %d: enable\n", irq);
+
+ if ( genirq_check(priv->genirq, irq) )
+ return DRVMGR_FAIL;
+
+ rtems_interrupt_disable(level);
+
+ /* Enable IRQ */
+ priv->irq->mask[0] |= (1<<irq); /* unmask interrupt source */
+
+ rtems_interrupt_enable(level);
+
+ return DRVMGR_OK;
+}
+
+int ambapp_tmtc_1553_int_mask(
+ struct drvmgr_dev *dev,
+ int irq)
+{
+ struct gr_tmtc_1553_priv *priv = dev->parent->dev->priv;
+ rtems_interrupt_level level;
+
+ DBG("TMTC-1553 IRQ %d: disable\n", irq);
+
+ if ( genirq_check(priv->genirq, irq) )
+ return DRVMGR_FAIL;
+
+ rtems_interrupt_disable(level);
+
+ /* Disable IRQ */
+ priv->irq->mask[0] &= ~(1<<irq); /* mask interrupt source */
+
+ rtems_interrupt_enable(level);
+
+ return DRVMGR_OK;
+}
+
+int ambapp_tmtc_1553_int_clear(
+ struct drvmgr_dev *dev,
+ int irq)
+{
+ struct gr_tmtc_1553_priv *priv = dev->parent->dev->priv;
+
+ if ( genirq_check(priv->genirq, irq) )
+ return DRVMGR_FAIL;
+
+ priv->irq->iclear = (1<<irq);
+
+ return DRVMGR_OK;
+}
+
+int ambapp_tmtc_1553_get_params(struct drvmgr_dev *dev, struct drvmgr_bus_params *params)
+{
+ struct gr_tmtc_1553_priv *priv = dev->parent->dev->priv;
+
+ /* Device name prefix pointer, skip /dev */
+ params->dev_prefix = &priv->prefix[5];
+
+ return 0;
+}
+
+void gr_tmtc_1553_print_dev(struct drvmgr_dev *dev, int options)
+{
+ struct gr_tmtc_1553_priv *priv = dev->priv;
+ struct pci_dev_info *devinfo = priv->devinfo;
+ uint32_t bar0, bar0_size;
+
+ /* Print */
+ printf("--- GR-TMTC-1553 [bus 0x%x, dev 0x%x, fun 0x%x] ---\n",
+ PCI_DEV_EXPAND(priv->pcidev));
+
+ bar0 = devinfo->resources[0].address;
+ bar0_size = devinfo->resources[0].size;
+
+ printf(" PCI BAR[0]: 0x%lx - 0x%lx\n", bar0, bar0 + bar0_size - 1);
+ printf(" IRQ REGS: 0x%x\n", (unsigned int)priv->irq);
+ printf(" IRQ: %d\n", devinfo->irq);
+ printf(" FREQ: %d Hz\n", priv->version->amba_freq_hz);
+ printf(" IMASK: 0x%08x\n", priv->irq->mask[0]);
+ printf(" IPEND: 0x%08x\n", priv->irq->ipend);
+
+ /* Print amba config */
+ if ( options & TMTC_1553_OPTIONS_AMBA ) {
+ ambapp_print(&priv->abus, 10);
+ }
+#if 0
+ /* Print IRQ handlers and their arguments */
+ if ( options & TMTC_1553_OPTIONS_IRQ ) {
+ int i;
+ for(i=0; i<16; i++) {
+ printf(" IRQ[%02d]: 0x%x, arg: 0x%x\n",
+ i, (unsigned int)priv->isrs[i].handler, (unsigned int)priv->isrs[i].arg);
+ }
+ }
+#endif
+}
+
+void gr_tmtc_1553_print(int options)
+{
+ struct pci_drv_info *drv = &gr_tmtc_1553_info;
+ struct drvmgr_dev *dev;
+
+ dev = drv->general.dev;
+ while(dev) {
+ gr_tmtc_1553_print_dev(dev, options);
+ dev = dev->next_in_drv;
+ }
+}
diff --git a/c/src/lib/libbsp/sparc/shared/spw/grspw_pci.c b/c/src/lib/libbsp/sparc/shared/spw/grspw_pci.c
deleted file mode 100644
index fce2fa8..0000000
--- a/c/src/lib/libbsp/sparc/shared/spw/grspw_pci.c
+++ /dev/null
@@ -1,132 +0,0 @@
-#include <ambapp.h>
-#include <rtems/libio.h>
-#include <grspw_pci.h>
-
-/* Select PCI driver */
-#define GRSPW_PCI
-
-#undef GRSPW_MAXDEVS
-#undef DEBUG_SPACEWIRE_ONOFF
-
-/* Only Malloced memory supported
- */
-#undef GRSPW_LOCAL_MEM
-
-/* memory must be aligned to a 128k boundary */
-unsigned int grspwpci_memarea_address;
-#define GRSPW_LOCAL_MEM_ADR grspwpci_memarea_address
-
-/* We have custom address tranlation for HW addresses */
-#define GRSPW_ADR_TO
-
-/* MEMAREA=>CPU used when reading descriptor buffer pointers,
- * they need to be translated from adresses used by GRSPW HW
- * into CPU readable addresses.
- *
- * NOT NEEDED AS GRSPW DRIVER USES INDEXES TO GET DESCRIPTOR
- * DATA POINTER ADDRESSES.
- */
-#undef GRSPW_ADR_FROM
-
-/* Set registered device name */
-#define GRSPW_DEVNAME "/dev/grspwpci0"
-#define GRSPW_DEVNAME_NO(devstr,no) ((devstr)[13]='0'+(no))
-
-/* Any non-static function will begin with */
-#define GRSPW_PREFIX(name) grspwpci##name
-
-/* do nothing, assume that the interrupt handler is called
- * setup externally calling b1553_interrupt_handler.
- */
-#define GRSPW_REG_INT(handler,irq,arg) \
- if ( grspw_pci_int_reg ) \
- grspw_pci_int_reg(handler,irq,arg);
-
-void (*grspw_pci_int_reg)(void *handler, int irq, void *arg) = 0;
-
-
-#ifdef GRSPW_ADR_TO
-/* Translate an address within the Memory Region (memarea) into an Hardware
- * device address. This address is put into hardware registers or descriptors
- * so that the hardware can access the Memory Region.
- * Example:
- * A local AMBA access at 0xe0000000 will translate into PCI address 0x40000000,
- * the PCI address 0x40000000 will translate into LEON-AMBA address 0x40000000.
- */
-unsigned int grspwpci_hw_address;
-static inline unsigned int memarea_to_hw(unsigned int addr) {
- /* don't translate? */
- if ( grspwpci_hw_address == 0xffffffff )
- return addr;
- return ((addr & 0x0fffffff) | grspwpci_hw_address);
-}
-#endif
-
-/* not used since BRM Core work with offsets */
-#ifdef GRSPW_ADR_FROM
-unsigned int grspwpci_cpu_access_address;
-static inline unsigned int hw_to_cpu(unsigned int addr) {
- /* don't translate? */
- if ( grspwpci_cpu_address == 0xffffffff )
- return addr;
- return ((addr & 0x0fffffff) | grspwpci_cpu_address);
-}
-#endif
-
-int grspwpci_interrupt_handler(int irq, void *arg);
-
-#include "grspw.c"
-
-/*
- *
- * memarea = preallocated memory somewhere, pointer to start of memory.
- * hw_address = how to translate a memarea address into an HW device AMBA address.
- */
-
-int grspw_pci_register(
- struct ambapp_bus *bus,
- unsigned int memarea,
- unsigned int hw_address
- )
-{
- /* Setup configuration */
-
- /* if zero the malloc will be used */
- grspwpci_memarea_address = memarea;
-
- grspwpci_hw_address = hw_address;
-
-#ifdef GRSPW_ADR_FROM
- grspwpci_cpu_address = memarea & 0xf0000000;
-#endif
-
- /* Register the driver */
- return GRSPW_PREFIX(_register)(bus);
-}
-
-/* Call this from PCI interrupt handler
- * irq = the irq number of the HW device local to that IRQMP controller
- *
- */
-int grspwpci_interrupt_handler(int irq, void *arg){
- grspw_interrupt( (GRSPW_DEV *)arg );
- return 0;
-}
-
-#if 0
-int grspw_pci_interrupt_handler(int irqmask){
- int i;
- unsigned int mask=0;
- /* find minor */
- for(i=0; i<spw_cores; i++){
- if ( (1<<SPW_PARAM(i).irq) & irqmask ){
- mask |= 1<<SPW_PARAM(i).irq;
- grspw_interrupt(i);
- /* more interrupts to scan for? */
- if ( irqmask & ~mask )
- return mask; /* handled */
- }
- }
- return mask;
-}
-#endif
diff --git a/c/src/lib/libbsp/sparc/shared/spw/grspw_rasta.c b/c/src/lib/libbsp/sparc/shared/spw/grspw_rasta.c
deleted file mode 100644
index b76d46a..0000000
--- a/c/src/lib/libbsp/sparc/shared/spw/grspw_rasta.c
+++ /dev/null
@@ -1,158 +0,0 @@
-#include <rtems.h>
-#include <grspw_rasta.h>
-
-/* Select PCI driver */
-#define GRSPW_PCI
-
-#undef GRSPW_MAXDEVS
-#undef DEBUG_SPACEWIRE_ONOFF
-/*#define DEBUG_SPACEWIRE_ONOFF*/
-/*
- * If USE_AT697_RAM is defined the RAM on the AT697 board will be used for DMA buffers (but rx message queue is always in AT697 ram).
- * USE_AT697_DMA specifies whether the messages will be fetched using DMA or PIO.
- *
- * RASTA_PCI_BASE is the base address of the GRPCI AHB slave
- *
- */
-
-#define USE_AT697_RAM 1
-#define USE_AT697_DMA 0
-#define RASTA_PCI_BASE 0xe0000000
-#define GRSPW_RASTA_MEM_OFF 0x21000
-
-/* Make GRSPW driver use malloced or static memory
- */
-#ifdef USE_AT697_RAM
-#undef GRSPW_STATIC_MEM
-#else
-#define GRSPW_STATIC_MEM
-#define GRSPW_CALC_MEMOFS(maxcores,corenum,ptr_mem_base,ptr_mem_end,ptr_bdtable_base) \
- grspw_rasta_calc_memoffs((maxcores),(corenum),(ptr_mem_base),(ptr_mem_end),(ptr_bdtable_base))
-#endif
-
-/* We have custom address tranlation for HW addresses */
-#define GRSPW_ADR_TO
-
-/* MEMAREA=>CPU used when reading descriptor buffer pointers,
- * they need to be translated from adresses used by GRSPW HW
- * into CPU readable addresses.
- *
- * NOT NEEDED AS GRSPW DRIVER USES INDEXES TO GET DESCRIPTOR
- * DATA POINTER ADDRESSES.
- */
-#undef GRSPW_ADR_FROM
-
-/* Set registered device name */
-#define GRSPW_DEVNAME "/dev/grspwrasta0"
-#define GRSPW_DEVNAME_NO(devstr,no) ((devstr)[15]='0'+(no))
-
-/* Any non-static function will begin with */
-#define GRSPW_PREFIX(name) grspwrasta##name
-
-/* do nothing, assume that the interrupt handler is called
- * setup externally calling grspw_interrupt_handler.
- */
-#define GRSPW_REG_INT(handler,irq,arg) \
- if ( grspw_rasta_int_reg ) \
- grspw_rasta_int_reg(handler,irq,arg);
-
-#define GRSPW_DONT_BYPASS_CACHE
-
-#ifdef GRSPW_ADR_TO
-/* Translate a address within the Memory Region (memarea) into an Hardware
- * device address. This address is put into hardware registers or descriptors
- * so that the hardware can access the Memory Region.
- * Example:
- * An local AMBA access at 0xe0000000 will translate into PCI address 0x40000000,
- * the PCI address 0x40000000 will translate into CPU-AMBA address 0x40000000.
- */
-static inline unsigned int memarea_to_hw(unsigned int addr) {
- return ((addr & 0x0fffffff) | RASTA_PCI_BASE);
-}
-#endif
-
-void (*grspw_rasta_int_reg)(void *handler, int irq, void *arg) = 0;
-
-#ifdef GRSPW_STATIC_MEM
-static int grspw_rasta_calc_memoffs(int maxcores, int corenum, unsigned int *mem_base, unsigned int *mem_end, unsigned int *bdtable_base);
-#endif
-
-void grspw_rasta_interrupt_handler(unsigned int status);
-
-void grspwrasta_interrupt_handler(int irq, void *pDev);
-
-#include "grspw.c"
-
-unsigned int grspw_rasta_memarea_address;
-
-/* Register RASTA GRSPW driver.
- *
- * memarea = preallocated memory somewhere, pointer to start of memory.
- */
-
-int grspw_rasta_register(
- struct ambapp_bus *bus,
- unsigned int ram_base
- )
-{
- /* Setup configuration */
-
- /* if zero the malloc will be used */
- grspw_rasta_memarea_address = ram_base + GRSPW_RASTA_MEM_OFF;
-
- /* Register the driver */
- return GRSPW_PREFIX(_register)(bus);
-}
-
-#if 0
-/* Call this from PCI interrupt handler, simply figures out
- * which GRSPW core was responsible for the IRQ (may be multiple).
- * v = status of the PCI/AMBA MCPU IRQ CTRL
- */
-void grspw_rasta_interrupt_handler(unsigned int status)
-{
- int minor;
-
- for(minor = 0; minor < spw_cores; minor++) {
- if (status & (1<<grspw_devs[minor].irq) ) {
- grspw_interrupt(&grspw_devs[minor]);
- }
- }
-}
-#endif
-
-void GRSPW_PREFIX(_interrupt_handler)(int irq, void *pDev)
-{
- grspw_interrupt(pDev);
-}
-
-
-#ifdef GRSPW_STATIC_MEM
-/*
- * --------------------------------------- <-
- * | Core1: BD TABLE 1 and 2 |
- * | Core2: BD TABLE 1 and 2 |
- * | Core3: BD TABLE 1 and 2 |
- * |-------------------------------------|
- * | Core1: rx data buf + rx header buf |
- * | Core2: rx data buf + rx header buf |
- * | Core3: rx data buf + rx header buf |
- * ---------------------------------------
- */
-static int grspw_rasta_calc_memoffs(int maxcores, int corenum, unsigned int *mem_base, unsigned int *mem_end, unsigned int *bdtable_base)
-{
- if ( maxcores > 3 )
- return -1;
-
- if ( bdtable_base )
- *bdtable_base = grspw_rasta_memarea_address + corenum*2*SPACEWIRE_BDTABLE_SIZE;
-
- if ( mem_base )
- *mem_base = grspw_rasta_memarea_address + coremax*2*SPACEWIRE_BDTABLE_SIZE + corenum*BUFMEM_PER_LINK;
-
- if ( mem_end )
- *mem_end = grspw_rasta_memarea_address + coremax*2*SPACEWIRE_BDTABLE_SIZE + (corenum+1)*BUFMEM_PER_LINK;
-
- return 0;
-}
-#endif
diff --git a/c/src/lib/libbsp/sparc/shared/uart/apbuart_pci.c b/c/src/lib/libbsp/sparc/shared/uart/apbuart_pci.c
deleted file mode 100644
index 9ea3967..0000000
--- a/c/src/lib/libbsp/sparc/shared/uart/apbuart_pci.c
+++ /dev/null
@@ -1,44 +0,0 @@
-#include <ambapp.h>
-#include <apbuart_pci.h>
-
-#undef DEBUG
-
-/* Set registered device name */
-#define APBUART_DEVNAME "/dev/apbupci0"
-#define APBUART_DEVNAME_NO(devstr,no) ((devstr)[12]='0'+(no))
-
-/* Any non-static function will begin with */
-#define APBUART_PREFIX(name) apbuartpci##name
-
-/* do nothing, assume that the interrupt handler is called
- * setup externally calling apbuartpci_interrupt_handler.
- */
-#define APBUART_REG_INT(handler,irq,arg) \
- if ( apbuart_pci_int_reg ) \
- apbuart_pci_int_reg(handler,irq,arg);
-
-void (*apbuart_pci_int_reg)(void *handler, int irq, void *arg) = 0;
-
-void apbuartpci_interrupt_handler(int irq, void *arg);
-
-/* AMBA Bus is clocked using the PCI clock (33.3MHz) */
-#define SYS_FREQ_HZ 33333333
-
-#include "apbuart.c"
-
-int apbuart_pci_register(struct ambapp_bus *bus)
-{
- /* Setup configuration */
-
- /* Register the driver */
- return APBUART_PREFIX(_register)(bus);
-}
-
-
-/* Call this from PCI interrupt handler
- * irq = the irq number of the HW device local to that IRQMP controller
- *
- */
-void apbuartpci_interrupt_handler(int irq, void *arg){
- apbuart_interrupt(arg);
-}
diff --git a/c/src/lib/libbsp/sparc/shared/uart/apbuart_rasta.c b/c/src/lib/libbsp/sparc/shared/uart/apbuart_rasta.c
deleted file mode 100644
index f6d561e..0000000
--- a/c/src/lib/libbsp/sparc/shared/uart/apbuart_rasta.c
+++ /dev/null
@@ -1,43 +0,0 @@
-#undef DEBUG
-
-#include <apbuart_rasta.h>
-
-/* Set registered device name */
-#define APBUART_DEVNAME "/dev/apburasta0"
-#define APBUART_DEVNAME_NO(devstr,no) ((devstr)[14]='0'+(no))
-
-/* Any non-static function will begin with */
-#define APBUART_PREFIX(name) apbuartrasta##name
-
-/* do nothing, assume that the interrupt handler is called
- * setup externally calling apbuartrasta_interrupt_handler.
- */
-#define APBUART_REG_INT(handler,irq,arg) \
- if ( apbuart_rasta_int_reg ) \
- apbuart_rasta_int_reg(handler,irq,arg);
-
-void (*apbuart_rasta_int_reg)(void *handler, int irq, void *arg) = 0;
-
-void apbuartrasta_interrupt_handler(int irq, void *arg);
-
-/* AMBA Bus is clocked using the RASTA internal clock (30MHz) */
-#define SYS_FREQ_HZ 30000000
-
-#include "apbuart.c"
-
-int apbuart_rasta_register(struct ambapp_bus *bus)
-{
- /* Setup configuration */
-
- /* Register the driver */
- return APBUART_PREFIX(_register)(bus);
-}
-
-
-/* Call this from RASTA interrupt handler
- * irq = the irq number of the HW device local to that IRQMP controller
- *
- */
-void apbuartrasta_interrupt_handler(int irq, void *arg){
- apbuart_interrupt(arg);
-}
--
1.7.0.4
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