RPI2 Cache configuration Was: Re: GSoC 2015: Raspberry Pi 2 Support

[Gedare Bloom]

On Thu, May 28, 2015 at 10:11 AM, Rohini Kulkarni <krohini1593 at gmail.com> wrote:
> Hi All,
>
> I have to implement the cache coherency support for Cortex A7. But for A7
> MPCore, unlike for A9, I am not able to find any register description for
> the Snoop Control Unit from the TRM.
> I need help here on how to proceed.
>
Based on 10 minutes from searching through the online TRM, I guess(?)
you need to set the pins for the ACE configuration as described in
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0464e/BABJECBF.html

See also: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0464f/BABBAAII.html

> Additionally for A9 there is a single bit for A9 in the Auxiliary Control
> Register which enables cache broadcast operations. The register format is
> different for A7 and again I am unable to find how to achieve the same for
> A7.
>
I think this is also controlled through the ACE.

> Thanks!
>
>
>